1999 May 31
17
Philips Semiconductors
Product specification
Digital video encoder
SAA7126H; SAA7127H
Table 21
Logic levels and function of CCRS
Table 22
Subaddress 61H
Table 23
Subaddress 62AH
CCRS1
CCRS0
DESCRIPTION
0
0
1
1
0
1
0
1
no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5
cross-colour reduction #1 active; for overall transfer characteristic see Fig.5
cross-colour reduction #2 active; for overall transfer characteristic see Fig.5
cross-colour reduction #3 active; for overall transfer characteristic see Fig.5
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
FISE
0
1
0
1
0
864 total pixel clocks per line; default after reset
858 total pixel clocks per line
NTSC encoding (non-alternating V component)
PAL encoding (alternating V component); default after reset
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4)
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4); default after reset
luminance gain for white
black 100 IRE; default after reset
luminance gain for white
black 92.5 IRE including 7.5 IRE set-up of black
PAL switch phase is nominal; default after reset
PAL switch phase is inverted compared to nominal if RTC is enabled (see Table 23)
DAC for CVBS in normal operational mode; default after reset
DAC for CVBS forced to lowest output voltage
DACs for R, G and B in normal operational mode
DACs for R, G and B forced to lowest output voltage; default after reset
PAL
SCBW
1
YGS
0
1
0
1
0
1
0
1
INPI
DOWNA
DOWNB
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
RTCE
0
1
no real-time control of generated subcarrier frequency; default after reset
real-time control of generated subcarrier frequency through SAA7151B or SAA7111; for
timing see Fig.13