1999 May 31
13
Philips Semiconductors
Product specification
Digital video encoder
SAA7126H; SAA7127H
Table 8
Subaddress 29H
Table 9
Subaddresses 2AH to 2CH
Table 10
Subaddress 2DH
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
REMARKS
BE
ending point of burst in clock cycles
PAL: BE = 29 (1DH); default after reset
NTSC: BE = 29 (1DH)
SRES
0
1
pin 19 is Real-Time Control Input (RTCI)
pin 19 is Sync Reset input (SRES)
a HIGH impulse resets synchronization of the
encoder (first field, first line)
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
CG
LSB of the respective bytes are encoded immediately after run-in, the MSBs of the
respective bytes have to carry the CRCC bits, in accordance with the definition of copy
generation management system encoding format.
copy generation data output is disabled; default after reset
copy generation data output is enabled
CGEN
0
1
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
BTRI
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC for BLUE output in 3-state mode (high-impedance)
DAC for BLUE output in normal operation mode; default after reset
DAC for GREEN output in 3-state mode (high-impedance)
DAC for GREEN output in normal operation mode; default after reset
DAC for RED output in 3-state mode (high-impedance)
DAC for RED output in normal operation mode; default after reset
DAC for CVBS output in 3-state mode (high-impedance)
DAC for CVBS output in normal operation mode; default after reset
RED output signal is switched to R DAC; default after reset
chrominance output signal is switched to R DAC
BLUE output signal is switched to B DAC; default after reset
CVBS output signal is switched to B DAC
if CSYNC = 0, CVBS output signal is switched to CVBS DAC; default after reset
if CSYNC = 0, luminance (VBS) output signal is switched to CVBS DAC
GREEN output signal is switched to G DAC; default after reset
luminance (VBS) output signal is switched to G DAC
GTRI
RTRI
CVBSTRI
CEN
CVBSEN
VBSEN0
VBSEN1