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參數(shù)資料
| 型號(hào)： | SAA7121 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Digital Video Encoder (ConDENC) |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 225K |
| 代理商： | SAA7121 |
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1997 Jan 06
26
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
Fig.10 RTCI timing.
handbook, full pagewidth
128
13
14
19
67
69 72 74
68
01
0
0
21
RTCI
HPLL
increment
FSCPLL increment
(1)
H/L transition
count start
4 bits
reserved
(7)
valid
sample
invalid
sample
not used in SAA7120/21
5 bits
reserved
(7)
8/LLC
MBH789
LOW
time slot:
(2)
(3)
(5)
(6)
(4)
(3) Reset bit: only from SAA7111 decoder.
(4) FISE bit: 0 = 50 Hz, 1 = 60 Hz.
(5) Odd/even bit: odd/even from external.
(6) Colour detection: 0 = no colour detected, 1 = colour detected.
(7) Reserved bits: 232 with 50 Hz systems, 229 with 60 Hz systems.
(1) SAA7111 provides (22:0) bits, resulting in 3 reserved bits before
sequence bit.
(2) Sequence bit
PAL: 0 = (R
Y) line normal, 1 = (R
Y) line inverted
NTSC: 0 = no change.
Explanation of RTCI data bits
1.
The ConDENC generates the subcarrier frequency out
of the FSCPLL increment if enabled (see item 6.).
The PAL bit indicates the line with inverted R - Y
component of colour difference signal.
If the reset bit is enabled
(RTCE = 1; DECPH = 1; PHRES = 00), the phase of
the subcarrier is reset in each line whenever the reset
bit of RTCI input is set to 1.
If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the
ConDENC takes this bit instead of the FISE bit in
subaddress 61H.
If the odd/even bit is enabled (RTCE = 1; DECOE = 1),
the ConDENC ignores its internally generated
odd/even flag and takes the odd/even bit from RTCI
input.
2.
3.
4.
5.
6.
If the colour detection bit is enabled (RTCE = 1;
DECCOL = 1) and no colour was detected (colour
detection bit = 0), the subcarrier frequency is
generated by the ConDENC. In the other case (colour
detection bit = 1) the subcarrier frequency is evaluated
out of FSCPLL increment.
If the colour detection bit is disabled (RTCE = 1;
DECCOL = 0), the subcarrier frequency is evaluated
out of FSCPLL increment, independent of the colour
detection bit of RTCI input.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7124HZ | Digital Video Encoder ECO-DENC |
| SAA7124 | Digital Video Encoder ECO-DENC |
| SAA7124H | Digital Video Encoder ECO-DENC |
| SAA7125 | Digital Video Encoder ECO-DENC |
| SAA7125H | Digital Video Encoder ECO-DENC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7121H | 制造商:NXP Semiconductors 功能描述: |
| SAA7121H/V2 | 制造商:NXP Semiconductors 功能描述: |
| SAA7121H/V2,518 | 功能描述:視頻 IC SAA7121H/QFP44/REEL13DP//V2 RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7121H/V2,557 | 功能描述:視頻 IC DIG VID ENCODER NTSC PAL RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7121H/V2557 | 制造商:NXP Semiconductors 功能描述:IC VIDEO ENCODER DIGITAL 44-QFP |
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