2
1
P
P
P
S
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Horizontal offset for slicer
Vertical offset for slicer
Field offset and MSBs for
horizontal and vertical offset
Reserved (for testing)
Header and data identification
(DID) code control
Sliced data identification (SDID)
code
Reserved
Slicer status byte 0 (read only)
Slicer status byte 1 (read only)
Slicer status byte 2 (read only)
Reserved
59
5A
5B
HOFF7
VOFF7
FOFF
HOFF6
VOFF6
RECODE
HOFF5
VOFF5
(1)
HOFF4
VOFF4
VOFF8
HOFF3
VOFF3
(1)
HOFF2
VOFF2
HOFF10
HOFF1
VOFF1
HOFF9
HOFF0
VOFF0
HOFF8
5C
5D
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
FVREF
(1)
DID5
DID4
DID3
DID2
DID1
DID0
5E
(1)
(1)
SDID5
SDID4
SDID3
SDID2
SDID1
SDID0
5F
60
61
62
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
FC8V
LN2
(1)
FC7V
F21_N
LN1
(1)
VPSV
LN8
LN0
(1)
PPV
LN7
DT3
(1)
CCV
LN6
DT2
(1)
LN5
DT1
(1)
LN4
DT0
(1)
LN3
(1)
63 to 7F
X port, I port and the scaler part: registers 80H to EFH
T
ASK INDEPENDENT GLOBAL SETTINGS
: 80H
TO
8FH
Global control 1
Reserved
80
(1)
SMOD
(1)
TEB
(1)
TEA
(1)
ICKS3
(1)
ICKS2
(1)
ICKS1
(1)
ICKS0
(1)
81 and
82
83
(1)
X port I/O enable and output
clock phase control
I port signal definitions
I port signal polarities
I port FIFO flag control and
arbitration
I port I/O enable, output clock
and gated clock phase control
Power save control
Reserved
Status information scaler part
(1)
(1)
XPCK1
XPCK0
(1)
XRQT
XPE1
XPE0
84
85
86
IDG01
ISWP1
VITX1
IDG00
ISWP0
VITX0
IDG11
ILLV
IDG02
IDG10
IG0P
IDG12
IDV1
IG1P
FFL1
IDV0
IRVP
FFL0
IDH1
IRHP
FEL1
IDH0
IDQP
FEL0
87
IPCK3
IPCK2
IPCK1
IPCK0
(1)
(1)
IPE1
IPE0
88
CH4EN
(1)
CH2EN
(1)
SWRST
(1)
DPROG
(1)
SLM3
(1)
(1)
SLM1
(1)
SLM0
(1)
89 to 8E
8F
(1)
XTRI
ITRI
FFIL
FFOV
PRDON
ERROF
FIDSCI
FIDSCO
REGISTER FUNCTION
SUB
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0