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參數(shù)資料
| 型號： | SAA7103 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital video encoder |
| 中文描述： | 數(shù)字視頻編碼器 |
| 文件頁數(shù)： | 53/76頁 |
| 文件大小： | 289K |
| 代理商： | SAA7103 |
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2001 Sep 25
53
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 86
Subaddress 96H
Table 87
Subaddress 97H
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
EFS
0
1
0
1
0
1
0
1
0
1
0
frame sync signal at pin FSVGC ignored in slave mode
frame sync signal at pin FSVGC accepted in slave mode
normal polarity of CBO signal (HIGH during active video)
inverted polarity of CBO signal (LOW during active video)
the SAA7102; SAA7103 is timing master to the graphics controller
the SAA7102; SAA7103 is timing slave to the graphics controller
if hardware cursor insertion is active, set LOW for non-interlaced input signals
if hardware cursor insertion is active, set HIGH for interlaced input signals
luminance sharpness booster disabled
luminance sharpness booster enabled
normal trigger event handling of the horizontal state machine, if the SAA7102;
SAA7103 is slave to HSVGC input
trigger event for horizontal state machine is shifted 128 PIXCLKs in advance, adapted
to a late HSVGC in slave mode
PCBN
SLAVE
ILC
YFIL
HSL
1
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
HFS
0
1
horizontal sync is directly derived from input signal (slave mode) at pin HSVGC
horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if
EFS is set HIGH)
vertical sync (field sync) is directly derived from input signal (slave mode) at
pin VSVGC
vertical sync (field sync) is derived from a frame sync signal (slave mode) at
pin FSVGC (only if EFS is set HIGH)
pin FSVGC is switched to input
pin FSVGC is switched to active output
polarity of signal on FSVGC in output mode (master mode) is active HIGH; rising edge
of the input signal is used in slave mode
polarity of signal on FSVGC in output mode (master mode) is active LOW; falling edge
of the input signal is used in slave mode
pin VSVGC is switched to input
pin VSVGC is switched to active output
polarity of signal on VSVGC in output mode (master mode) is active HIGH; rising edge
of the input signal is used in slave mode
polarity of signal on VSVGC in output mode (master mode) is active LOW; falling edge
of the input signal is used in slave mode
VFS
0
1
OFS
0
1
0
PFS
1
OVS
0
1
0
PVS
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7103E | Digital video encoder |
| SAA7103H | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:48; Connector Shell Size:36; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| SAA7104E | Digital video encoder |
| SAA7105E | Digital video encoder |
| SAA7104H | GT 38C 38#12 PIN PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7103E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7103E/V4,518 | 功能描述:視頻 IC PC DENC WO MACROVISION LICENSE RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7103E/V4,557 | 功能描述:視頻 IC PC DENC WO MACROVISION LICENSE RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7103H | 制造商:NXPSEM 功能描述: |
| SAA7103H/V4,518 | 功能描述:視頻 IC PC DENC WO MACROVISION LICENSE RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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