- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372111 > SAA55xx (NXP Semiconductors N.V.) Standard TV microcontrollers with On-Screen Display (OSD)(用于屏幕顯示的標準TV微控制器) PDF資料下載
參數(shù)資料
| 型號： | SAA55xx |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Standard TV microcontrollers with On-Screen Display (OSD)(用于屏幕顯示的標準TV微控制器) |
| 中文描述： | 微控制器與標準電視屏幕顯示（OSD）（用于屏幕顯示的標準電視微控制器） |
| 文件頁數(shù)： | 36/80頁 |
| 文件大?。?/td> | 311K |
| 代理商： | SAA55XX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
1999 Oct 27
36
Philips Semiconductors
Preliminary specification
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
15.2
Tuning Pulse Width Modulator (TPWM)
The device has a single 14-bit PWM that can be used for
Voltage Synthesis Tuning. The method of operation is
similar to the normal PWM except the repetition period is
42.66
μ
s.
15.2.1
TPWM
CONTROL
Two SFRs are used to control the TPWM, they are TDACL
and TDACH. The TPWM is enabled by setting the
TPWE bit in the TDACH SFR. The most significant bits
TD<13:7> alter the high period between 0 and 42.33
μ
s.
The 7 least significant bits TD<6:0> extend certain pulses
by a further 0.33
μ
s, e.g. if TD<6:0> = 01H then
1 in 128 periods will be extended by 0.33
μ
s, if
TD<6:0> = 02H then 2 in 128 periods will be extended.
TheTPWMwillnotstarttooutputanewvalueuntilTDACH
has been written to. Therefore, if the value is to be
changed, TDACL should be written before TDACH.
15.3
Software ADC (SAD)
Four successive approximation Analog-to-Digital
Converterscanbeimplementedinsoftwarebymakinguse
of the on-board 8-bit Digital-to-Analog Converter and
Analog Comparator.
15.3.1
SAD
CONTROL
The control of the required analog input is done using the
channel select bits CH<1:0> in the SAD SFR, this selects
the required analog input to be passed to one of the inputs
of the comparator. The second comparator input is
generated by the DAC whose value is set by the bits
SAD<7:0> in the SAD and SADB SFRs. A comparison
between the two inputs is made when the start compare
bit ST in the SAD SFR is set, this must be at least one
instruction cycle after the SAD<7:0> value has been set.
The result of the comparison is given on VHI one
instruction cycle after the setting of ST.
15.3.2
SAD I
NPUT
V
OLTAGE
The external analog voltage that is used for comparison
with the internally generated DAC voltage does not have
the same voltage range. The DAC has a lower reference
level of V
SSA
and an upper reference level of V
SSP
.
The resolution of the DAC voltage with a nominal value is
3.3
256
≈
13 mV. The external analog voltage has a lower
value equivalent to V
SSA
and an upper value equivalent to
V
DDP
V
tn
,whereV
tn
isthethresholdvoltageforanN type
Metal Oxide Semiconductor transistor. The reason for this
is that the input pins for the analog signals (P3.0 to P3.3)
are 5 V tolerant for normal port operations, i.e. when not
used as analog input. To protect the analog multiplexer
and comparator circuitry from the 5 V, a series transistor is
used to limit the voltage. This limiting introduces a voltage
drop equivalent to V
tn
(
≈
0.6 V) on the input voltage.
Therefore, for an input voltage in the range V
DDP
to
V
DDP
V
tn
the SAD returns the same comparison value.
15.3.3
SAD DC C
OMPARATOR
M
ODE
The SAD module incorporates a DC Comparator mode
which is selected using the DC_COMP control bit in the
SADB SFR. This mode enables the microcontroller to
detect a threshold crossing at the input to the selected
analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
P3.3/ADC3) of the Software ADC. A level sensitive
interrupt is generated when the analog input voltage level
at the pin falls below the analog output level of the SAD
DAC.
This mode is intended to provide the device with a
wake-up mechanism from Power-down or Idle mode when
a key-press on the front panel of the TV is detected.
The following software sequence should be used when
utilizing this mode for Power-down or Idle:
1.
Disable INT1 using the IE SFR.
2.
Set INT1 to level sensitive using the TCON SFR.
3.
Set the DAC digital input level to the desired threshold
level using SAD/SADB SFRs and select the required
input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
P3.3/ADC3) using CH<1:0> in the SAD SFR.
4.
Enter DC Compare mode by setting the DC_COMP
enable bit in the SADB SFR.
5.
Enable INT1 using the IE SFR.
6.
Enter Power-down or Idle mode. Upon wake-up the
SAD should be restored to its conventional operating
mode by disabling the DC_COMP control bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA5500PS | Standard TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的標準型TV控制器) |
| SAA5501PS | Standard TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的標準型TV控制器) |
| SAA5502PS | Standard TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的標準型TV控制器) |
| SAA5520 | Standard TV Microcontrollers with On-Screen Display(OSD) |
| SAA5520PS | Standard TV Microcontrollers with On-Screen Display(OSD) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA5603 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| SAA5645 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced TV microcontrollers with On-Screen Display OSD |
| SAA5645HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced TV microcontrollers with On-Screen Display OSD |
| SAA5647 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced TV microcontrollers with On-Screen Display OSD |
| SAA5647HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced TV microcontrollers with On-Screen Display OSD |
發(fā)布緊急采購，3分鐘左右您將得到回復。