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參數(shù)資料
| 型號(hào)： | SAA5565PS |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced TV microcontrollers with On-Screen Display (OSD)(帶全屏顯示的增強(qiáng)型TV控制器) |
| 中文描述： | 與微控制器在強(qiáng)化電視屏幕顯示（OSD）（帶全屏顯示的增強(qiáng)型電視控制器） |
| 文件頁(yè)數(shù)： | 10/100頁(yè) |
| 文件大小： | 371K |
| 代理商： | SAA5565PS |
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2000 Feb 23
10
Philips Semiconductors
Preliminary specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
7
MICROCONTROLLER
The functionality of the microcontroller used on this device
is described here with reference to the industry standard
80C51 microcontroller. A full description of its functionality
can be found in “Handbook IC20, 80C51-Based 8-bit
Microcontrollers”.
7.1
Microcontroller features
80C51 microcontroller core standard instruction set and
timing
1
μ
s machine cycle
Maximum 128K
×
8-bit Program ROM
Maximum of 12K
×
8-bit Auxiliary RAM
InterruptControllerforindividualenable/disablewithtwo
level priority
Two 16-bit Timer/Counter registers
Watchdog Timer
Auxiliary RAM page pointer
16-bit Data pointer
Idle and Power-down mode
29 general I/O lines
Eight 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analog signals
One 14-bit PWM for Voltage Synthesis Tuner (VST)
control
8-bit ADC with 4 multiplexed inputs
2 high current outputs for directly driving LEDs etc.
I
2
C byte level bus interface with dual ports.
8
MEMORY ORGANIZATION
The device has the capability of a maximum of 128-kbyte
Program ROM and 12-kbyte Data RAM internally.
8.1
ROM bank switching
The 64-kbyte device has a continuous address space from
0 to 64 kbytes. The 128-kbyte memory is arranged in four
banks of 32 kbytes. One of the 32-kbyte banks is common
and is always addressable. The other three banks
(Bank 0, Bank 1 and Bank 2) can be accessed by
selecting the right bank via the SFR ROMBK bits; see
Table 2.
The ROM bank switching is handled and supported by the
compiler and linker development tools.
Table 2
ROM bank selection
8.2
Security bits - program and verify
SAA55xx devices have a set of security bits allied with
each section of the device, i.e. Program ROM, Character
ROM and Packet 26 ROM. The security bits are used to
prevent the ROM from being overwritten once
programmed, and also the contents being verified once
programmed. The security bits are one-time
programmable and
cannot
be erased.
The SAA55xx memory and security bits are structured as
shown in Fig.5. The SAA55xx security bits are set as
shown in Fig.6 for production programmed devices and
are set as shown in Fig.7 for production blank devices.
8.3
RAM organisation
The internal Data RAM is organised into two areas, Data
memory and Special Function Registers (SFRs) as shown
in Fig.8.
8.4
Data memory
The Data memory is 256
×
8 bits and occupies the
addressrange00H to FFHwhenusingindirectaddressing
and 00H to 7FH when using direct addressing. The SFRs
occupy the address range 80H to FFH and are accessible
using direct addressing only.
The lower 128 bytes of Data memory are mapped as
shown in Fig.9. The lowest 24 bytes are grouped into
4 banksof8 registers,thenext16 bytesabovetheregister
banks form a block of bit addressable memory space.
The upper 128 bytes is not allocated for any special area
or functions.
Table 3
Bank selection
ROMBK1 ROMBK0 0 TO 32-kbyte 32 TO 64-kbyte
0
0
1
1
0
1
0
1
common
common
common
reserved
Bank 0
Bank 1
Bank 2
reserved
RS1
RS0
BANK
0
0
1
1
0
1
0
1
Bank 0
Bank 1
Bank 2
Bank 3
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