2000 Feb 23
79
Philips Semiconductors
Preliminary specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
19.12.1 D
EFINING CHARACTERS
The DRC RAM is mapped into the 80C51 RAM address
space and starts at location 8800H. The character matrix
is 12 bits wide and therefore requires two bytes to be
written for each word, the first byte (even addresses),
addresses the lower 8 bits and the lower nibble of the
second byte (odd addresses) addresses the upper 4 bits.
For characters of 9, 10 or 16 lines high the pixel
information starts in the first address and continues
sequentially for the required number of address.
Characters of 13 lines high are defined with an initial offset
of 1 address, this is to allow for correct generation of
fringing across boundaries of clustered characters see
Fig.39. The characters continue sequentially for 13 lines
after which a further line can again be used for generation
of correct fringing across boundaries of clustered
characters.
19.13 Display synchronization
The horizontal and vertical synchronizing signals from the
TV deflection are used as inputs. Both signals can be
inverted before being delivered to the Phase Selector
section.
CC:
The polarity is controlled using either VPOL or HPOL
bits in the MMR Text Position Vertical.
TXT:
The TXT1.H POLARIY and TXT1.V POLARITY bits
control the polarity.
Alinelocked12 MHzclockisderivedfromthe12 MHzfree
running oscillator by the Phase Selector. This line locked
clock is used to clock the whole of the display block.
The horizontal and vertical sync signals are synchronized
with the 12 MHz clock before being used in the display
section.
19.14 Video/data switch (Fast Blanking) polarity
The polarity of the Video/data (Fast Blanking) signal can
be inverted. The polarity is set with the VDSPOL bit in the
MMR RGB Brightness.
Table 30
Fast Blanking signal polarity
19.15 Video/Data switch adjustment
To take into account the delay between the RGB values
and the VDS signal due to external buffering, the VDS
signal can be moved in relation to the RGB signals.
The VDSsignalcanbesettobeeitheraclockcyclebefore
or after the RGB signal, or coincident with the RGB signal.
This is done using VDEL<2:0> in the MMR Configuration.
Fig.39 13 line high DRCs character format.
handbook, halfpage
line
number
line 13 from
character above
line 1 from
character below
top left
pixel
MSB
LSB
MBK975
HEX
440
003
00C
030
0C0
300
C00
C00
300
0C0
030
00C
003
000
1A8
000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
fringing
top line
bottom right
pixel
bottom line
fringing
line not used
VDSPOL
VDS
CONDITION
0
0
1
1
1
0
0
1
RGB display
Video display
RGB display
Video display