參數(shù)資料
型號: SAA5530
廠商: NXP Semiconductors N.V.
英文描述: Enhanced TV microcontrollers with On-Screen Display OSD
中文描述: 與微控制器在強化電視屏幕顯示OSD
文件頁數(shù): 89/100頁
文件大?。?/td> 371K
代理商: SAA5530
2000 Feb 23
89
Philips Semiconductors
Preliminary specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
Table 35
I
2
C-bus characteristics
Notes
1.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IL(min)
of the SCL
signal) in order to bridge the undefined region of the falling edge of SCL.
The maximum f
HD;DAT
has only to be met if the device does not stretch the LOW period t
LOW
of the SCL signal.
A fast-mode I
2
C-bus device can be used in a standard mode I
2
C-bus system but the requirement t
SU;DAT
250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
r(max)
+ t
SU;DAT
= 1000 + 250 +1250 ns (according to the standard mode I
2
C-bus specification) before the SCL line
is released.
C
b
= total capacitance of one bus line in pF.
2.
3.
4.
SYMBOL
PARAMETER
FAST-MODE I
2
C-bus
UNIT
MIN.
MAX.
f
SCL
t
BUF
t
HD;STA
SCL clock frequency
bus free time between a STOP and START condition
hold time (repeated) START condition. After this period, the
first clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START condition
data hold time; notes 1 and 2
data set-up time, note 3
rise time of both SDA and SCL signals; note 4
fall time of both SDA and SCL signals; note 4
set-up time for STOP condition
capacitive load for each bus line
0
1.3
0.6
400
kHz
μ
s
μ
s
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
r
t
f
t
SU;STO
C
b
1.3
0.6
0.6
0
100
20
20
0.6
0.9
300
300
400
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
pF
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