參數(shù)資料
型號(hào)： SAA5491PS
廠商： NXP Semiconductors N.V.
英文描述： DPST MINIATURE POWER RELAY
中文描述： 經(jīng)濟(jì)圖文電視和電視微控制器
文件頁(yè)數(shù)： 35/68頁(yè)
文件大小： 612K
代理商： SAA5491PS
1997 Jul 07
35
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
8.9
Packet 26 processing
One of the uses of packet 26 is to transmit characters
which are not in the basic teletext character set. The family
automatically decodes packet 26 data and, if a character
corresponding to that being transmitted is available in the
character set, automatically writes the appropriate
character code into the correct location in the teletext
memory. This is not a full implementation of the packet 26
specification allowed for in level 2 teletext, and so is often
referred to as level 1.5.
By convention, the packets 26 for a page are transmitted
before the normal packets. To prevent the default
character data overwriting the packet 26 data the device
incorporates a mechanism which prevents packet 26 data
from being overwritten. On the SAA5291,SAA5291A and
SAA5491 devices this mechanism is disabled when the
Spanish national option is detected as the Spanish
transmission system sends even parity (i.e. incorrect)
characters in the basic page locations corresponding to
the characters sent via packet 26 and these will not
overwrite the packet 26 characters anyway. The special
treatment of Spanish national option is prevented if
TXT12.ROM VER R4 is logic 0 or if the TXT8.DISABLE
SPANISH is set.
Packet 26 data is processed regardless of the
TXT1.EXT PKT OFF bit, but setting theTXT1.X26 OFF
disables packet 26 processing.
The TXT8.Pkt 26 received bit is set by the hardware
whenever a character is written into the page memory by
the packet 26 decoding hardware. The flag can be reset by
writing a logic 0 into the SFR bit.
8.10
VPS
When the TXT0. VPS ON bit is set, any VPS data present
on line 16, field 0 of the CVBS signal at the input of the
teletext decoder is error checked and stored in row 25,
block 0 for SAA5291, SAA5291A, SAA5491 and row 25,
block 9 for SAA5296/7, SAA5296/7A, SAA5496/7 of the
basic page memory. The device automatically detects
whether teletext or VPS is being transmitted on this line
and decodes the data appropriately.
Each VPS byte in the memory consists of 4 bi-phase
decoded data bits (bits 0 to 3), a bi-phase error flag (bit 4)
and three 0s (bits 5 to 7).
The TXT13.VPS Received bit is set by the hardware
whenever VPS data is acquired. The flag can be reset by
writing a logic 0 into the SFR bit. Full details of the VPS
system can be found in “Specification of the Domestic
Video Programme Delivery Control System (PDC); EBU
Tech. 3262-E”
Table 16
VPS data storage
ROW
COLUMN
0 TO 9
10 TO 11
12 TO 13
14 TO 15
16 TO 17
18 TO 19
20 TO 21
22 TO 23
Row 25 Teletext page header data
VPS
byte 11
VPS
byte 12
VPS
byte 13
VPS
byte 14
VPS
byte 15
VPS
byte 4
VPS
byte 5
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