1997 Jul 07
9
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
LRGBREF
B
G
R
VDS
HSYNC
31
32
33
34
35
36
39
40
41
42
43
45
DC input voltage to define the output HIGH level on the RGB pins.
Pixel rate output of the BLUE colour information.
Pixel rate output of the GREEN colour information.
Pixel rate output of the RED colour information.
Video/data switch push-pull output for dot rate fast blanking.
Schmitt trigger input for a TTL level version of the horizontal sync pulse; the
polarity of this pulse is programmable by register bit TXT1.H POLARITY.
Schmitt trigger input for a TTL level version of the vertical sync pulse;
the polarity of this pulse is programmable by register bit TXT1.V POLARITY.
+5 V analog power supply.
+5 V teletext power supply.
Crystal oscillator ground.
12 MHz crystal oscillator input.
12 MHz crystal oscillator output.
If the reset input is HIGH for at least 3 machine cycles (36 oscillator periods)
while the oscillator is running, the device is reset; this pin should be
connected to V
DDM
via a 2.2
μ
F capacitor.
+5 V microcontroller power supply.
Port
1: 8-bit open-drain bidirectional port with alternate functions.
VSYNC
37
47
V
DDA
V
DDT
OSCGND
XTALIN
XTALOUT
RESET
38
39
40
41
42
43
49
51
56
57
58
59
V
DDM
P1.0/INT1
P1.1/T0
P1.2/INT0
P1.3/INT1
P1.6/SCL
P1.7/SDA
P1.4
P1.5
44
45
46
47
48
49
50
51
52
62
63
64
60
61
65
66
67
68
P1.0/INT1 is external interrupt 1 which can be triggered on the rising and
falling edge of the pulse.
P1.1/T0 is the counter/timer 0.
P1.2/INT0 is external interrupt 0.
P1.3/T1 is the counter/timer 1.
P1.6/SCL is the serial clock input for the I
2
C-bus.
P1.7/SDA is the serial data port for the I
2
C-bus.
Positive reference voltage for software driven ADC.
Negative reference voltage for software driven ADC.
Read control signal to external Data Memory.
Write control signal to external Data Memory.
Enable signal for external Program Memory.
External latch enable signal; active HIGH.
Control signal used to select external (LOW) or internal (HIGH) Program
Memory.
Address lines A0 to A7 multiplexed with data lines D0 to D7.
Address lines A8 to A15.
REF+
REF
RD
WR
PSEN
ALE
EA
50
19
10
11
17
18
13
AD0 to AD7
A8 to A15
69 to 76
55 to 52,
35 to 32
SYMBOL
PIN
DESCRIPTION
SDIP52
QFP80