February 1995
14
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
Slave receiver.
The advantages of the bit-level I
2
C-bus hardware,
compared with a full software I
2
C-bus implementation are:
The hardware can generate the SCL pulse
Testing a single bit (RBF or WBF respectively) is
sufficient as a check for error-free transmission.
The bit-level I
2
C-bus hardware operates on serial bit level
and performs the following functions:
Filtering the incoming serial data and clock signals
Recognizing the START condition
Generating a serial interrupt request SI after reception of
a START condition and the first falling edge of the serial
clock
Recognizing the STOP condition
Recognizing a serial clock pulse on the SCL line
Latching a serial bit on the SDA line (SDI)
Stretching the SCL LOW period of the serial clock to
suspend the transfer of the next serial data bit
Setting Read Bit Finished (RBF) when the SCL clock
pulse has finished and Write Bit Finished (WBF) if there
is no arbitration loss detected (i.e. SDA = logic 0 while
SDO = logic 1)
Setting a serial clock LOW-to-HIGH detected (CLH) flag
Setting a Bus Busy (BB) flag on a START condition and
clearing this flag on a STOP condition
Releasing the SCL line and clearing the CLH, RBF and
WBF flags to resume transfer to the next serial data bit
Generating an automatic clock if the single bit data
register S1BIT is used in master mode.
The following functions must be done in software:
Handling the I
2
C-bus START interrupts
Converting serial data to parallel data when receiving
Converting parallel data to serial data when transmitting
Comparing the received slave address with its own
address
Interpreting the acknowledge information
Guarding the I
2
C-bus status if RBF or WBF = logic 0.
Additionally, if acting as master:
Generating START and STOP conditions
Handling bus arbitration
Generating serial clock pulses if S1BIT is not used.
Three SFRs support the function of the bit-level I
2
C-bus
hardware, they are S1INT, S1BIT and S1SCS.
LED
SUPPORT
Port pins P0.5 and P0.6 have a 10 mA current sinking
capability to enable LEDs to be driven directly.
PWM DAC
S
The SAA5290 has six 6-bit PWM DACs and one14-bit
PWM DAC. These allow direct control of other parts of the
television.
The low resolution 6 bit DACs are controlled by their
corresponding SFR (PWM0 to PWM5) and are connected
as alternative outputs of Port P2. The port bit
corresponding to the PWM should be set to logic 1 for
correct operation of the PWM.
Table 7
Special Function Registers PWM0 to PWM5
If the PWE bit for a particular port is set to logic 1, the PWM
is active and controls its assigned port pin. If the PWE bit
is set to logic 0 the corresponding port pin is controlled by
the bit in the corresponding port register for that port.
The output of the PWM is a pulse of period 21.33
μ
s with
a duty cycle determined by the binary value, PV5 to PV0,
multiplied by 0.33
μ
s. The 14 bit PWM is controlled with
SFR registers TDACL and TDACH.
Table 8
Special Function Register TDACL
Table 9
Special Function Register TDACH
If the PWE bit is set to logic 1, the TPWM is active and
controls Port P2.0. If the PWE bit is set to logic 0 the port
pin is controlled by the bit in the corresponding port
register for P2.0.
The output of the TPWM is a pulse of period 42.66
μ
s with
a duty cycle determined by the binary value, TD13 to TD7,
multiplied by 0.33
μ
s.
D7
D6
D5
D4
D3
D2
D1
D0
PWE
PV5
PV4
PV3
PV2
PV1
PV0
D7
D6
D5
D4
D3
D2
D1
D0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
D7
D6
D5
D4
D3
D2
D1
D0
PWE
TD13 TD12 TD11
TD10 TD9
TD8