參數(shù)資料
型號(hào)： SAA4978H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Picture Improved Combined Network PICNIC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁(yè)數(shù)： 43/56頁(yè)
文件大?。?/td> 296K
代理商： SAA4978H
1999 May 03
43
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
SAA4978H
Notes
1.
With AGC at
3 dB, Y full ADC range is obtained at V
i
= 1.41 V; with AGC at 6 dB, Y full ADC range is obtained at
V
i
= 0.5 V; with AGC at
3 dB, U full ADC range is obtained at V
i
= 1.89 V; with AGC at 6 dB, U full ADC range is
obtained at V
i
= 0.67 V; with AGC at
3 dB, V full ADC range is obtained at V
i
= 1.48 V; with AGC at 6 dB, V full ADC
range is obtained at V
i
= 0.52 V; at AGC attenuation more than 0 dB, where the input signal has an amplitude above
the nominal value, the input processing and transfer function may have decreased specification.
2.
DNL is defined as deviation of the code length from the average code length in LSB;
q
q
av
1
–
: 0.99LSB means no missing code.
3.
Measurements taken using video analyzer VM700A at YUV output, control bit SEL_1FH (address 391H) set to
logic 1, internal analog filters off, AGC gain (addresses 302H, 303H and 304H) set to 074H, digital processing in
between, digital filters off, sampling frequency of 16 MHz.
Supply Voltage Ripple Rejection (SVRR) is a relative variation of the full scale analog input for a supply variation of
0.25 V over a frequency range from 20 Hz to 50 kHz. This includes
1
2
f
V
, f
V
, 2f
V
, f
H
and 2f
H
which are major load
frequencies.
Measurements carried out using Modulation Domain Analyzer HP53310A after change of control bit PLL_OPEN
(address 376H) from logic 1 to logic 0 (open to closed-circuit). Control bits PLL_CK (address 375H) set to logic 0.
Control bits PLL_CD (address 375H) set to 7.
The outputs are able to drive an external low-pass filter without slewing. In f
H
and 2f
H
this filter is of the type as
described in Fig.6. For calculating an output filter the typical output impedance is also given in Fig.6.
The output levels for U and V have 1 dB reserve headroom in case of a 75% saturated colour bar. The maximum
levels are 1.33 V + 1 dB = 1.49 V for U and 1.05 V + 1 dB = 1.18 V for V. Due to 1 dB headroom the typical AGC
setting to obtain 0 dB from input to output for U and V is 83.
The AC characteristics are in accordance with the I
2
C-bus specification for fast mode (clock frequency maximum
400 kHz). Information about the I
2
C-bus can be found in the brochure “I
2
C-bus and how to use it”(order number
9398 393 40011).
4.
5.
6.
7.
8.
Analog Y, U and V output filters (3rd-order linear phase filter with notch at f
CLK
)
f
(
3dB)
α
(0.5)
3 dB down frequency
attenuation at
1
2
f
CLK
(16 MHz)
stop band attenuation
(after notch)
notch frequency
group delay
group delay tolerance
between channels
11.3
7
11.7
8
12.1
MHz
dB
α
sb
32
dB
f
notch
t
d(g)
t
d(g)(tol)
tuned to
1
2
f
CLK
at 8 MHz signal frequency
30.6
26
32
28
33.4
31
5
MHz
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DNL
max
-----------------
(
)
=
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