參數(shù)資料
型號(hào)： SAA4970T
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： Economical video processing IC ECOBENDIC
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO56
封裝： PLASTIC, SOT-190-1, VSOP-56
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 179K
代理商： SAA4970T
1996 Oct 25
13
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
If a write to ‘SAMPLE AQUI and DISPL’ is done, MUXE will
be loaded with the momentary CNT_D contents.
An interrupt can be generated on a pre-defined display line
(Counter D-interrupt-Display-b) by writing its line number
to the ‘set CD_intDb’ register. If the interrupt is not desired,
the register should be filled with a value above the
maximum number of display lines. The value 1FFH is
suggested.
If VI2 is used as an output, the falling edge can be
activated by addressing the ‘start flyback’ register and the
rising edge by addressing the ‘start scan’ register. In the
‘horizontal display block’ a pulse is generated with the
‘VHU register/comparator’. This pulse is used for the
timing of the edges within the lines. This gives the ability to
determine the interlace of the display and is continuously
variable. It is useful to use the display interrupt to trigger
the microcontroller for issuing the flyback and scan edges
in a certain display line.
G
ATES BLOCK
The internal signals ‘Gate Acquisition 1’ (GA1), ‘Gate
Acquisition 2’ (GA2), ‘Gate Acquisition 3’ (GA3) and ‘Gate
Display’ (GD) are fed through shift stages, which are
programmed to shift the rising and falling edges 0, 1, 2 or
3 input clock periods. For GA1, GA2 and GA3 the shift is
in CK1 periods; for GD the shift is in CK2 periods.
The construction of the shifts makes it possible to generate
the gate outputs with higher resolution than the other
signals. If MC1 =
1
4
CK1 and MC2 =
1
4
CK2, any position
of the edges is possible with a resolution of CK1 and CK2
clock period.
A
CQUISITION AND DISPLAY INTERRUPTS BLOCKS
As described in the acquisition and display vertical blocks,
on programmed positions of CNT_B, CNT_C and CNT_D
interrupts are generated. Also, as described in the
horizontal acquisition block, an interrupt may be generated
on a rising edge of the PIP signal.
The PIP related interrupt and the ‘gate input, CNT_C’
related interrupt can be enabled or disabled by bits in the
PLL control register.
The status of each interrupt is separately held in a flip-flop.
The interrupt status flip-flops can all be monitored by
reading MUXC.
To reset any of the interrupts, the flip-flops can be reset
individually by addressing their reset interrupt address.
The interrupts are grouped into two output signals: IT1 is a
combination of all acquisition related interrupts, while IT2
is the only display related interrupt.
A
CQUISITION AND DISPLAY CLOCK BLOCKS
The CK1 and CK2 input clock signals are divided into div1
or div4 signals (internal clock signals), where div1 in only
meant for testing purposes. The divided clocks are
multiplexed to MC1 and MC2.
The multiplexer select states for MC1 and MC2 are
programmed in the internal control register.
M
ICROCONTROLLER INTERFACE BLOCK
The microcontroller interface consists of an addressing, a
read and a write part.
The
addressing
is performed with an address latch, that
latches the address/data bus while ‘a(chǎn)ddress latch enable’
is active (HIGH).
Writing
data to any destination in the ECO-PSP consists
of two activities:
1.
The address in the address latch is converted to an
enable signal for the destination in question. This
enable is activated while WRN is active (LOW).
2.
The 8-bit data on the address/data bus is merged with
a 9th bit, which is the highest bit (bit 7) of the address
latch. This resulting 9-bit data is sent to registers in the
various blocks. Most registers only use 8 bits of data,
in that case the 9th bit is a ‘don’t care’.
Writing to 7 addresses simultaneously is possible by
supplying an address in the range of 00H to 07H. All the
destinations in the column of that address in the write table
are then supplied with the same data.
The destinations in the ECO-PSP may be: 9-bit registers,
8-bit registers, counter resets, interrupt resets, gate output
selects and the acquisition and display function.
Reading
data from one of the 7 readable registers also
consists of two activities:
1.
The address in the address latch is converted to a
multiplexer setting for the source in question.
2.
The 8-bit data from the source 3-state enabled to the
address/data bus. If a 9-bit register is read out, the
highest bit (bit 8) is coded in the MUXC source.
The seven sources in the ECO-PSP are described in the
read table.
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