
1998 Mar 10
6
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
Notes
1.
2.
3.
4.
5.
See Table 1.
All V
SSDI
pins are internally connected.
All V
DDDI
pins are internally connected.
All V
DDDE
pins are internally connected.
All V
SSDE
pins are internally connected.
V
SSDE
SYSCLK
V
DDDE
V
DDA
CLKI
CLKO
V
SSDA
ACLK
V
SSDE
TDI
38
39
40
41
42
43
44
45
46
47
E
H
H
A
B
S
O
S
S
I
O
S
I
S
I
digital ground for I/O cells; note 5
programmable system clock output
digital supply voltage for I/O cells (+3.3 V); note 4
analog supply voltage for crystal oscillator (+3.3 V)
oscillator input
oscillator output
digital ground for crystal oscillator
audio clock input for master mode
digital ground for I/O cells; note 5
boundary scan test data input (this pin should be pulled HIGH for
normal operation)
boundary scan test mode select input (this pin should be pulled HIGH
for normal operation)
boundary scan test clock input
boundary scan test reset input (this pin should be pulled LOW for
normal operation)
boundary scan test data output
digital supply voltage for internal logic and memories (+3.3 V); note 3
digital ground for internal logic and memories; note 2
word select input for ports 0 and 1 (I
2
S-bus)
serial data begin input for port 0 (I
2
S-bus)
serial data input for port 0 (I
2
S-bus)
serial data input for port 1 (I
2
S-bus)
serial clock input for ports 0 and 1 (I
2
S-bus)
digital ground for internal logic and memories; note 2
digital supply voltage for internal logic and memories (+3.3 V); note 3
hardware reset
select address input (I
2
C-bus)
serial clock input; external pull-up to +5 V (I
2
C-bus)
serial data input/output; external pull-up to +5 V (I
2
C-bus)
TMS
48
B
I
TCK
TRST
49
50
B
B
I
I
TDO
V
DDDI
V
SSDI
WSI
SDBI
SDI0
SDI1
SCKI
V
SSDI
V
DDDI
RESET
ADDR
SCL
SDA
51
52
53
54
55
56
57
58
59
60
61
62
63
64
B
A
A
A
A
A
C
A
C
D
O
S
S
I
I
I
I
I
S
S
I
I
I
I/O
SYMBOL
PIN
DRIVE/
LOAD
(1)
TYPE
DESCRIPTION