參數(shù)資料
型號(hào)： SAA2503HT
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： MPEG2 audio decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
文件頁(yè)數(shù)： 8/20頁(yè)
文件大小： 139K
代理商： SAA2503HT
1997 Jul 02
8
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
FUNCTIONAL DESCRIPTION
Operating modes
The SAA2503 can operate in 2 modes.
Stand-alone (mode 4)
In this mode (modC = 1, modB = 0 and modA = 0) the
SAA2503 boots itself from the internal program ROM after
power-up and can start decoding when a decoding mode
has been selected via the I
2
C-bus.
Booting via the I
2
C-bus (mode 7)
In this mode (modC = 1, modB = 1 and modA = 1) the
SAA2503 starts executing an internal boot program that
will receive 1536 bytes via the I
2
C-bus and then write
those to an on-chip program RAM.
This mode allows the standard behaviour (I/O interfaces,
additional processing) to be modified as specified in the
stand-alone mode.
Decoding modes
The SAA2503 has the following decoding modes:
MPEG decoding (48 kHz DVD; 44.1 kHz VCD) IEC 958
LPCM
MPEG decoding (48 kHz DVD; 44.1 kHz VCD) IEC 958
BITSTR
LPCM CD-DA (44.1 kHz)
LPCM down-sampling DVD (96 kHz: 4 channel input;
48 kHz 2 channel output)
LPCM DVD (48 kHz: 8 channel input; 2 channel output).
System clock
The preferred system clock to be applied to the EXTAL pin
of the SAA2503 is 27 MHz if booted in mode 4
(stand-alone operation).
The internal PLL multiplies this clock by a factor of 3 to
obtain an 81 MHz internal clock.
If using another external clock frequency it is advisable to
ensure that:
The internal PLL is disabled during booting when
f
clk(ext)
> 27 MHz
That 10 MHz < (f
clk(ext)
×
3) < 81 MHz.
INTERFACING TO THE A/V SPLITTER
Serial audio interface
The serial audio interface can be configured as an I
2
S-bus
interface and when required, as Quad I
2
S interface.
The signal received via the I
2
S-bus is an encoded audio
bitstream in accordance with IEC 1937, or LPCM.
Table 1
Pinning of the I
2
S-bus interface
Notes
1.
SCKT is equal to SCKR when the I
2
S-bus format is the format of the input signal. When Quad I
2
S-bus is used
SCKT =
1
4
SCKR.
The maximum allowed clock frequency for SCK is
1
3
f
clk
(f
clk
is the internal clock generated by the PLL of the
SAA2503).
2.
PINS
DESCRIPTION
PIN NUMBER
DIRECTION
SDI0
SDI1
SDO0
SDO1
SDO2
SCKR
WSR
SDB
SCKT
WST
high impedance
serial data
serial data
serial data
serial data
I
2
S-bus clock; notes 1 and 2
word select receive
serial data begin
I
2
S-bus clock; notes 1 and 2
word select transmit
67
66
57
56
55
61
65
76
59
60
not used
input/output
output
not used
not used
input
input
input
input
input
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