參數(shù)資料
型號: SAA2022GP
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Tape formatting and error correction for the DCC system
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: PLASTIC, SOT-208A, QFP-64
文件頁數(shù): 19/52頁
文件大?。?/td> 208K
代理商: SAA2022GP
February 1994
19
Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
Fig.13 DRAM refresh cycle.
MEA704 - 1
MCLK
RASN
CASN
D0...D3
A0...A7 (A8)
OEN
WEN
1 refresh cycle = 651 ns
ROW
Tape deck capstan control interface
SPEED
This signal is a pulse width modulated output that may be
used to control the tape deck capstan. The period of the
SPEED signal is 41.66
μ
s and the nominal duty cycle is
50%.
There are 4 modes of operation for the SPEED signal
which can be selected by the programmed settings of
μ
CSPD (microcontroller capstan speed), ENFREG
(enable frequency regulation) and ENEFREG (enable
extended frequency regulation) flags.
SPDF
If
μ
CSPD = logic 0 this pin outputs a pulse width
modulated measurement of the main data channel bit
rates and may be used in combination with the SPEED
signal to control the tape deck capstan. The period of the
SPDF signal is 5.2
μ
s. The duty cycle of SPDF can vary
from 0% at +6.5% deviation to 100% at
6.5% deviation. If
the deviation = 0% then the duty cycle of SPDF is 50%.
Microcontroller Interface
LTREF
The SAA2022 divides time into segments of 42.67 ms
nominal duration which are counted in modulo 4. The
LTREF active LOW output pin can be connected directly to
the interrupt input of the microcontroller and indicates the
start of a time segment. It goes LOW for 5.2
μ
s once every
42.66 ms and can be used for generating interrupts. Note
if a resync occurs then the time between the occurrences
of LTREF can vary. The function and programming of the
other interface lines LTCNT0, LTCNT1, LTEN, LTCLK and
LTDATA are described in the pinning and programming
sections.
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