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參數(shù)資料
| 型號： | SA9025 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | 900 MHz transmit modulator and 2.2 GHz fractional-N synthesizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 X 1.40 MM, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大小： | 134K |
| 代理商： | SA9025 |
Philips Semiconductors
Objective specification
SA9025
900 MHz transmit modulator and 2.2 GHz
fractional–N synthesizer
1997 Aug 01
20
SR01454
REFERENCE R
MAIN M
VCO CYCLES
N
N
N+1
N
N+1
DETECTOR
OUTPUT
ACCUMULATOR
CONTENTS
2
4
1
3
0
FRACTIONAL
COMPENSATION
CURRENT
OUTPUT ON
PHP, PHI
PULSE
WIDTH
MODULATION
PULSE LEVEL
MODULATION
mA
μ
A
Figure 10.
Waveforms for NF = 2; Fraction = 0.4
Figure 10 shows that for a proper fractional compensation, the area
of the fractional compensation current pulse must be equal to the
area of the charge pump ripple output.
The fractional compensation current is derived from the main charge
pump in that it will follow all the current scaling through external
resistor setting, programming or speedup operation.
For a given pump,
|comp
|pump
128
x
5Fdac
Where:
Icomp is the compensation current, Ipump is the pump current, Fdac
is the fractional DAC value and FRD is the fractional accumulator
value.
The theoretical value for Fdac would then be: 128 for Fmod = 1
(modulo 5) and 80 for Fmod = 0 (modulo 8).
When the serial input A word is loaded, the output circuits are in the
“speedup mode” as long as the STROBE is H, otherwise the
“normal mode” is active.
Lock Detect
The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than
reference inputs XTAL1,2. The LOCK condition is also fulfilled when
the relative counter is disabled (PD
main
= ‘0’ or PD
aux
= ‘0’) for the
main or auxiliary counter, respectively. Lock indication when PD
main
= PD
aux
= ‘0’.
1 cycle on the
Functional Description of Offset Loop, Modulator
and Power Control
Transmit Offset Synthesizer
The transmit offset phase locked loop portion of the SA9025 design
consists of the following functional blocks: reference oscillator,
limiters, phase detector,
÷
M, IF VCO and passive loop filter.
Harmonic contents of this signal are attenuated by an LP filter. The
output of the IF VCO is also divided by N and compared with the
reference oscillator in the phase detector.
Reference Oscillator
This Oscillator is used to generate the reference frequency together
with an external crystal and varicap. The output is internally routed
to three buffers and a phase comparator. It is possible to run the
oscillator as an amplifier from an external reference signal (TCXO).
Phase Detector and Charge Pump
The phase comparator is used to compare the output of the divider
with the reference. It provides an output proportional to the phase
difference between the divided down VCO and the reference. This
VCO. The phase detector is a Gilbert multiplier cell type, having a
linear output from 0 to
π
(
π
/2
±
π
/2), followed by a charge pump. The
charge pump peak output current is programmable to 6.4mA via the
use of an external resistor.
A preliminary design analysis has been performed with the following
loop parameters:
A lock detect signal is provided and ANDed together with lock detect
signals from both the main channel synthesizer and auxiliary
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