參數(shù)資料
型號(hào)： SA702N
廠商： NXP SEMICONDUCTORS
元件分類： 諧振器
英文描述： Divide by: 64/65/72 triple modulus low power ECL prescaler
中文描述： SA700 SERIES, PRESCALER, PDIP8
封裝： 0.300 INCH, PLASTIC, MO-001AN, SOT-97-1, DIP-8
文件頁(yè)數(shù)： 3/7頁(yè)
文件大?。?/td> 80K
代理商： SA702N
Philips Semiconductors RF Communications Products
Product specification
SA702
Divide by: 64/65/72 triple modulus low power
ECL prescaler
June 17, 1993
4
DC ELECTRICAL CHARACTERISTICS
The following DC specifications are valid for T
A
= 25
°
C and V
CC
= 3.0V; unless otherwise stated. Test circuit Figure 1.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNITS
MIN
2.7
MAX
6.0
V
CC
I
CC
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
Power supply voltage range
Supply current
Output high level
Output low level
MC1 input high threshold
MC1 input low threshold
MC2 input high threshold
MC2 input low threshold
MC1 input high current
MC1 input low current
MC2 input high current
MC2 input low current
f
IN
= 1GHz, input level = 0dBm
No load
I
OUT
= 1.2mA
V
4.5
mA
V
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
V
CC
-1.4
V
CC
-2.6
2.0
–0.3
2.0
–0.3
V
CC
0.8
V
CC
0.8
50
V
MC1
= V
CC
= 6V
V
MC1
= 0V, V
CC
= 6V
V
MC2
= V
CC
= 6V
V
MC2
= 0V, V
CC
= 6V
0.1
–30
0.1
–30
–100
50
–100
AC ELECTRICAL CHARACTERISTICS
These AC specifications are valid for f
IN
= 1GHz, input level = 0dBm, V
CC
= 3.0V and T
A
= 25
°
C; unless otherwise stated. Test circuit Fig. 1.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNITS
MIN
0.05
0
MAX
2.0
1.1
1.1
V
IN
f
IN
Input signal amplitude
1
Input signal frequency
1000pF input coupling
Direct coupled input
2
1000pF input coupling
DC measurement
V
CC
= 5.0V
V
CC
= 3.0V
V
P-P
GHz
GHz
k
V
P-P
V
P-P
ns
ns
ns
R
ID
V
O
Differential input resistance
Output voltage
5
1.6
1.2
t
S
t
H
t
PD
Modulus set-up time
1
Modulus hold time
1
Propagation time
5
0
10
NOTES:
1. Maximum limit is not tested, however, it is guaranteed by design and characterization.
2. For f
IN
< 50MHz, minimum input slew rate of 32V/
μ
s is required.
DESCRIPTION OF OPERATION
The SA702 comprises a frequency divider
circuit implemented using a divide by 4 or 5
synchronous prescaler followed by a 5 stage
synchronous counter, see BLOCK
DIAGRAM. The normal operating mode is for
MC1 (Modulus Control) to be set high and
MC2 input to be set low in which case the
circuit comprises a divide by 64. For divide
by 65 the MC1 singal is forced low, causing
the prescaler circuit to switch into divide by 5
operation for the last cycle of the
synchronous counter. For divide by 72, MC2
is set high configuring the prescaler to divide
by 4 and the counter to divide by 18. A truth
table for the modulus values is given below:
Table 1.
Modulus
64
65
72
72
MC1
1
0
0
1
MC2
0
0
1
1
For minimization of propagation delay effects,
the second divider circuit is synchronous to
the divide by 4/5 stage output.
The prescaler input is positive edge sensitive,
and the output at the final count is a falling
edge with propagation delay t
PD
relative to
the input. The rising edge of the output
occurs at the count 32 with delay t
PD
.
The MC1 and MC2 inputs are TTL
compatible threshold inputs operating at a
reduced input current. CMOS and low
voltage interface capability are allowed.
The prescaler input is differential and ECL
compatible. The output is differential ECL
compatible.
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