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參數(shù)資料
| 型號： | SA7025DK |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Low-voltage 1GHz fractional-N synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1000 MHz, PDSO20 |
| 封裝： | PLASTIC, SOT-266, SSOP-20 |
| 文件頁數(shù)： | 14/22頁 |
| 文件大?。?/td> | 304K |
| 代理商： | SA7025DK |
Philips Semiconductors
Product specification
SA7025
1GHz low-voltage Fractional-N synthesizer
1996 Aug 6
14
REFERENCE R
MAIN N
DETECTOR
OUTPUT
CONTENTS
ACCUM.
FRACTIONAL
COMPCURRENT
N
N
N + 1
N
N + 1
2
4
1
3
0
PULSE-WIDTH
MODULATION
OUTPUT ON
PHP, PHI
PULSE-LEVEL
MODULATION
mA
μ
A
TIME
VCO CYCLES
SR00608
Figure 9. Waveforms for NF = 2, Fraction = 0.4
Lock Detect
The output LOCK is H when the auxiliary phase detector AND the
main phase detector indicates a lock condition. The lock condition
is defined as a phase difference of less than +1 cycle on the
reference input REF_IN. The lock condition is also fulfilled when the
relative counter is disabled (EM = “0” or respectively EA = “0”) for
the main, respectively auxiliary counter.
Test Modes
The lock output is selectable as f
REF
, f
AUX
, f
MAIN
and lock. Bits T1
and T0 of the E word control the selection (see Figures 6 and 10).
If T1 = T0 = Low, or if the E-word is not sent, the lock output is
configured as the normal lock output described in the Lock Detect
section.
If T1 = Low and T0 = High, the lock output is configured as f
REF
.
The signal is the buffered output of the reference divider NR and the
3-bit binary counter SM. The f
REF
signal appears as normally low
and pulses high whenever the divider reaches terminal count from
the value programmed into the NR and SM registers. The f
REF
signal can be used to verify the divide ratio of the Reference divider.
If T1 = High and T0 = Low, the lock output is configured as f
AUX
.
The signal is normally high and pulses low whenever the divider
reaches terminal count from the value programmed into the NA and
PA registers. The f
AUX
signal can be used to verify the divide ratio
of the Auxiliary divider.
If T1 = High and T0 = High, the lock output is configured as f
MAIN
.
The signal is the buffered output of the MAIN divider. The f
MAIN
signal appears as normally high and pulses low whenever the
divider reaches terminal count from the value programmed into the
NM1, NM2 or NM3 registers. The f
MAIN
signal can be used to verify
the divide ratio of the MAIN divider and the prescaler.
相關PDF資料 |
PDF描述 |
|---|---|
| SA7026 | 1.3GHz low voltage fractional-N dual frequency synthesizer |
| SA7026DH | 1.3GHz low voltage fractional-N dual frequency synthesizer |
| SA702 | Divide by: 64/65/72 triple modulus low power ECL prescaler |
| SA702D | Divide by: 64/65/72 triple modulus low power ECL prescaler |
| SA702N | Divide by: 64/65/72 triple modulus low power ECL prescaler |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SA7026 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3GHz low voltage fractional-N dual frequency synthesizer |
| SA7026DH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3GHz low voltage fractional-N dual frequency synthesizer |
| SA702D | 制造商:NXP Semiconductors 功能描述: 制造商: 功能描述: 制造商:undefined 功能描述: |
| SA702N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Divide by: 64/65/72 triple modulus low power ECL prescaler |
| SA703 | 制造商:Datak Corporation 功能描述:Precision ScrewDriver Set |
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