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參數(shù)資料
| 型號(hào)： | SA701 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Divide by: 128/129-64/65 dual modulus low power ECL prescaler |
| 中文描述： | 除以：128/129-64/65雙模預(yù)分頻器低功耗ECL |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 82K |
| 代理商： | SA701 |
Philips Semiconductors RF Communications Products
Product specification
SA701
Divide by: 128/129-64/65 dual modulus low power
ECL prescaler
June 17, 1993
4
DC ELECTRICAL CHARACTERISTICS
The following DC specifications are valid for T
A
= 25
°
C and V
CC
= 3.0V; unless otherwise stated. Test circuit Figure 1.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNITS
MIN
2.7
MAX
6.0
V
CC
I
CC
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
Power supply voltage range
Supply current
Output high level
Output low level
MC input high threshold
MC input low threshold
SW input high threshold
SW input low threshold
MC input high current
MC input low current
SW input high current
SW input low current
f
IN
= 1GHz, input level = 0dBm
No load
I
OUT
= 1.2mA
V
4.5
mA
V
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
V
CC
-1.4
V
CC
-2.6
2.0
–0.3
2.0
–0.3
V
CC
0.8
V
CC
0.8
50
V
MC
= V
CC
= 6V
V
MC
= 0V, V
CC
= 6V
V
SW
= V
CC
= 6V
V
SW
= 0V, V
CC
= 6V
0.1
–30
35
–0.1
–100
100
–50
AC ELECTRICAL CHARACTERISTICS
The following AC specifications are valid for V
CC
= 3.0V, f
IN
= 1GHz, input level = 0dBm, T
A
= 25
°
C; unless otherwise stated. Test circuit Fig. 1.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNITS
MIN
0.05
0
MAX
2.0
1.1
1.1
V
IN
f
IN
Input signal amplitude
1
Input signal frequency
1000pF input coupling
Direct coupled input
2
1000pF input coupling
DC measurement
V
CC
= 5.0V
V
CC
= 3.0V
V
P-P
GHz
GHz
k
V
P-P
V
P-P
ns
ns
ns
R
ID
V
O
Differential input resistance
Output voltage
5
1.6
1.2
t
S
t
H
t
PD
Modulus set-up time
1
Modulus hold time
1
Propagation time
5
0
10
NOTES:
1. Maximum limit is not tested, however, it is guaranteed by design and characterization.
2. For f
IN
< 50MHz, minimum input slew rate of 32V/
μ
s is required.
DESCRIPTION OF OPERATION
The SA701 comprises a frequency divider
circuit implemented using a divide by 4 or 5
synchronous prescaler followed by a 5 stage
synchronous counter, see BLOCK
DIAGRAM. The normal operating mode is for
SW (Modulus Set Switch) input to be set low
and MC (Modulus Control) input to be set
high in which case the circuit comprises a
divide by 128. For divide by 129 the MC
signal is forced low, causing the prescaler
circuit to switch into divide by 5 operation for
the last cycle of the synchronous counter.
Similarly, for divide by 64 and 65 the SA701
will generate those respective moduli with the
SW signal forced high, in which the fourth
stage of the synchronous divider is
bypassed. A truth table for the modulus
values is given below:
Table 1.
Modulus
128
129
64
65
MC
1
0
1
0
SW
0
0
1
1
For minimization of propagation delay effects,
the second divider circuit is synchronous to
the divide by 4/5 stage output.
The prescaler input is positive edge sensitive,
and the output at the final count is a falling
edge with propagation delay t
PD
relative to
the input. The rising edge of the output
occurs at the count 64 for modulus 128/129
or count 32 for modulus 64/65 with delay t
PD
.
The SW input is not designed for
synchronous switching.
The MC and SW inputs are TTL compatible
threshold inputs operating at a reduced input
current. CMOS and low voltage interface
capability are allowed. The SW input has an
internal pull-down simplifying modulus group
selection. With SW open the divide by
128/129 mode is selected and with SW
connected to V
CC
divide by 64/65 is selected.
The prescaler input is differential and ECL
compatible. The output is single-ended ECL
compatible.
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相關(guān)代理商/技術(shù)參數(shù) |
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| SA701/DF3 | 制造商:Hirose 功能描述: 制造商:Hirose 功能描述:SA701/DF3 |
| SA701/DF3(61) | 制造商:Hirose 功能描述:903-4507-7-61 EACH 制造商:Hirose 功能描述:SA701/DF3(61) |
| SA701/DF3(62) | 制造商:Hirose 功能描述:903-4507-7-62 EACH 制造商:Hirose 功能描述:SA701/DF3(62) |
| SA701/DF3(63) | 制造商:Hirose 功能描述:903-4507-7-63 EACH 制造商:Hirose 功能描述:SA701/DF3(63) |
| SA701/DF3(64) | 制造商:Hirose 功能描述:903-4507-7-64 EACH 制造商:Hirose 功能描述:SA701/DF3(64) |
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