參數(shù)資料
型號(hào): SA639
廠商: NXP Semiconductors N.V.
英文描述: Low voltage mixer FM IF system with filter amplifier and data switch
中文描述: 低電壓中頻濾波放大器和數(shù)據(jù)系統(tǒng),混頻器調(diào)頻開關(guān)
文件頁(yè)數(shù): 5/16頁(yè)
文件大?。?/td> 226K
代理商: SA639
Philips Semiconductors
Product specification
SA639
Low voltage mixer FM IF system with filter amplifier
and data switch
1998 Feb 10
5
AC ELECTRICAL CHARACTERISTICS
(Continued)
LIMITS
SA639
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MIN
-3
σ
+3
σ
MAX
Post detection filter amplifier
Amplifier 3dB bandwidth
AC coupled: R
L
= 10k
,
C
L
= 33pF
AC coupled: R
L
= 10k
,
V
OUT DC
= 1.6V
AC coupled: R
L
= 10k
,
C
L
= 33pF
11.7
12.8
13.8
MHz
Amplifier gain
-0.2
dB
Slew rate
2.4
V/
μ
s
Input resistance
Input capacitance
Output impedance
Output load resistance
Output load capacitance
1
DC output level
2
Data switch
DC input voltage range
3
AC input swing
Input impedance
Input capacitance
Output load resistance
Through Mode
(Pin 12 = LOW)
AC voltage gain
4
Output drive capability
Slew rate
Static offset voltage
5
300
k
pF
k
pF
V
3
150
800
AC coupled
AC coupled
5
30
1.7
1.5
1.682
1.718
1.9
1.2
1.6
400
2.0
V
mV
P-P
k
pF
100
5
500
-1.5
dB
mA
V/
μ
s
mV
Sink/source, V
OUT DC
= 1.6V
V
OUT DC
= 1.6V
V
IN DC
= 1.2 to 2.0V
V
IN DC
= 1.4 to 2.0V;
V
CC
= 3.0 to 5.0V;
RF level = -70 to -40 dBm
V
IN DC
= 1.4 to 2.0V;
V
CC
= 3.0 to 5.0V;
RF level = -40 to -5 dBm
3
>14.0
0.30
-0.6
1.2
±
5
Dynamic offset voltage
2, 6
-7
+7
mV
-10
+10
Tri-State Mode
(Pin 12 = HIGH)
Output leakage current
NOTES:
1. Includes filter feedback capacitance, comparator input capacitance. PCB stray capacitances and switch input capacitance.
2. Demodulator output DC coupled with Post Detection Filter Amplifier input and the demodulator tank exactly tuned to center frequency.
3. Includes DC offsets due to frequency offsets between Rx and Tx carrier and demodulator tank offset due to mis-tuning.
4. With a 400mV
P-P
sinusoid at 600kHz driving Pin 10. Output load resistance 500
in series with 10nF.
5. With a DC input and capacitor in the RC load fully charged.
6. The switch is closed every 10ms for a duration of 40
μ
s. The DC offset is determined by calculating the difference of 2 DC measurements,
which are determined as follows: 1) The first DC value is measured at the integrating capacitor of the switch when the switch is in the closed
position immediately before it opens. The value to be measured is in the middle of the peak-to-peak excursion of the superimposed
sine-wave. (DClow + (DChigh – DClow)/2). 2) The second DC value (calculated as above) is measured at Pin 11 immediately after the
switch opens, and is the DC value which gives the largest DC offset to the first DC measurement within a 400
μ
s DECT burst. Minimum and
maximum limits are not tested, however, they are guaranteed by design and characterization using an optimized layout and application
circuit.
7. Standard deviations are measured based on application of 60 parts.
V
OUT DC
= 1.2 to 2.0V
9.5
20
30.5
100
nA
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