參數(shù)資料
型號(hào): SA630
廠商: NXP Semiconductors N.V.
英文描述: Single pole double throw (SPDT) switch(單刀雙擲開關(guān))
中文描述: 單刀雙擲(SPDT)開關(guān)(單刀雙擲開關(guān))
文件頁數(shù): 4/14頁
文件大?。?/td> 282K
代理商: SA630
Philips Semiconductors
Product specification
SA630
Single pole double throw (SPDT) switch
1997 Nov 07
4
AC ELECTRICAL CHARACTERISTICS
1
- D PACKAGE
V
DD
= +5V, T
A
= 25
°
C; unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
SA630
UNITS
MIN
TYP
MAX
S
21
, S
12
Insertion loss (ON channel)
DC - 100MHz
500MHz
900MHz
1
1.4
2
2.8
dB
S
21
, S
12
Isolation (OFF channel)
2
10MHz
100MHz
500MHz
900MHz
70
24
80
60
50
30
dB
S
11
, S
22
Return loss (ON channel)
DC - 400MHz
900MHz
20
12
dB
S
11
, S
22
Return loss (OFF channel)
DC - 400MHz
900MHz
17
13
dB
t
D
t
r
, t
f
Switching speed (on-off delay)
50% TTL to 90/10% RF
20
ns
Switching speeds (on-off rise/fall time)
90%/10% to 10%/90% RF
5
ns
Switching transients
165
mV
P-P
dBm
P
-1dB
IP
3
IP
2
1dB gain compression
DC - 1GHz
+18
Third-order intermodulation intercept
100MHz
+33
dBm
Second-order intermodulation intercept
100MHz
+52
dBm
NF
Noise figure (Z
O
= 50
)
100MHz
900MHz
1.0
2.0
dB
NOTE:
1. All measurements include the effects of the D package SA630 Evaluation Board (see Figure 4B). Measurement system impedance is 50
.
2. The placement of the AC bypass capacitor is critical to achieve these specifications. See the applications section for more details.
AC ELECTRICAL CHARACTERISTICS
1
- N PACKAGE
V
DD
= +5V, T
A
= 25
°
C; all other characteristics similar to the D-Package, unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
SA630
UNITS
MIN
TYP
MAX
S
21
, S
12
Insertion loss (ON channel)
DC - 100MHz
500MHz
900MHz
1
1.4
2.5
dB
S
21
, S
12
Isolation (OFF channel)
10MHz
100MHz
500MHz
900MHz
58
68
50
37
15
dB
NF
Noise figure (Z
O
= 50
)
100MHz
900MHz
1.0
2.5
dB
NOTE:
1. All measurements include the effects of the N package SA630 Evaluation Board (see Figure 4C). Measurement system impedance is 50
.
APPLICATIONS
The typical applications schematic and printed circuit board layout of
the SA630 evaluation board is shown in Figure 4. The layout of the
board is simple, but a few cautions need to be observed. The input
and output traces should be 50
. The placement of the AC bypass
capacitor is extremely criticalif a symmetric isolation between the
two channels is desired. The trace from Pin 7 should be drawn back
towards the package and then be routed downwards. The capacitor
should be placed straight down as close to the device as practical.
For better isolation between the two channels at higher frequencies,
it is also advisable to run the two output/input traces at an angle.
This also minimizes any inductive coupling between the two traces.
The power supply bypass capacitor should be placed close to the
device. Figure 10 shows the frequency response of the SA630.
The loss matching between the two channels is excellent to 1.2GHz
as shown in Figure 13.
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