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參數(shù)資料
| 型號： | SA624 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High performance low power FM IF system with high-speed RSSI |
| 中文描述： | IF系統(tǒng)的高性能與低功耗調(diào)頻高速的RSSI |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 161K |
| 代理商： | SA624 |
Philips Semiconductors
Product specification
SA624
High performance low power FM IF system with
high-speed RSSI
1997 Nov 07
7
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NE624 TEST CIRCUIT
SA624
MUTE
AUDIO
OUT
RSSI
DATA
OUT
8
7
6
5
4
3
2
1
SA602A
+6V
100nF
10nF
47pF
22pF
100nF
5.6pF
44.545
3rd OVERTURE
XTAL
SFG455A3
C–MSG
FILTER
455kHz
Q=20
SFG455A3
+6V
V
CC
4V
10pF
3V
2V
1V
–0
–20
–40
–60
–
–80
10
100
1k
10k
100k
–120
–100
NE602 RF INPUT (dBm) (50
)
–80
–60
–40
–20
A
NE624 IF INPUT (
μ
V) (1500
)
(
+
AUDIO
RSSI (VOLTS)
THD + NOISE
AM (80% MOD)
NOISE
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
22pF
1nF
to
1.3
μ
H
5.5
μ
6.8
μ
F
0.21
to
0.28
μ
H
100k
0.1
μ
F
SR00444
Figure 5. Typical Application Cellular Radio (45MHz to 455kHz)
CIRCUIT DESCRIPTION
The SA624 is a very high gain, high frequency device. Correct
operation is not possible if good RF layout and gain stage practices
are not used. The SA624 cannot be evaluated independent of
circuit, components, and board layout. A physical layout which
correlates to the electrical limits is shown in Figure 3. This
configuration can be used as the basis for production layout.
The SA624 is an IF signal processing system suitable for IF
frequencies as high as 21.4MHz. The device consists of two limiting
amplifiers, quadrature detector, direct audio output, muted audio
output, and signal strength indicator (with output characteristic). The
sub-systems are shown in Figure 4. A typical application with
45MHz input and 455kHz IF is shown in Figure 5.
IF Amplifiers
The IF amplifier section consists of two log-limiting stages. The first
consists of two differential amplifiers with 39dB of gain and a small
signal bandwidth of 41MHz (when driven from a 50
source). The
output of the first limiter is a low impedance emitter follower with
1k
of equivalent series resistance. The second limiting stage
consists of three differential amplifiers with a gain of 62dB and a
small signal AC bandwidth of 28MHz. The outputs of the final
differential stage are buffered to the internal quadrature detector.
One of the outputs is available at Pin 9 to drive an external
quadrature capacitor and L/C quadrature tank.
Both of the limiting amplifier stages are DC biased using feedback.
The buffered output of the final differential amplifier is fed back to the
input through 42k
resistors. As shown in Figure 4, the input
impedance is established for each stage by tapping one of the
feedback resistors 1.6k
from the input. This requires one
additional decoupling capacitor from the tap point to ground.
42k
15
16
1
1.6k
40k
V+
70014
7k
SR00445
Figure 6. First Limiter Bias
Because of the very high gain, bandwidth and input impedance of
the limiters, there is a very real potential for instability at IF
frequencies above 455kHz. The basic phenomenon is shown in
Figure 8. Distributed feedback (capacitance, inductance and
radiated fields)
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