
Philips Semiconductors
Product specification
SA572
Programmable analog compandor
1998 Nov 03
6
Rectifier
The rectifier is a full-wave design as shown in Figure 5. The input
voltage is converted to current through the input resistor R
2
and
turns on either Q
5
or Q
6
depending on the signal polarity. Deadband
of the voltage to current converter is reduced by the loop gain of the
gain block A
2
. If AC coupling is used, the rectifier error comes only
from input bias current of gain block A
2
. The input bias current is
typically about 70nA. Frequency response of the gain block A
2
also
causes second-order error at high frequency. The collector current
of Q
6
is mirrored and summed at the collector of Q
5
to form the full
wave rectified output current I
R
. The rectifier transfer function is
I
R
V
IN
V
REF
R
2
(4)
If V
IN
is AC-coupled, then the equation will be reduced to:
I
RAC
V
IN
(AVG)
R
2
The internal bias scheme limits the maximum output current I
R
to be
around 300
μ
A. Within a
±
1dB error band the input range of the rectifier
is about 52dB.
V
IN
V
REF
V+
A2
+
–
R2
Q6
Q5
D7
IR
VIN
VREF
R2
SR00698
Figure 5. Simplified Rectifier Schematic
Buffer Amplifier
In audio systems, it is desirable to have fast attack time and slow
recovery time for a tone burst input. The fast attack time reduces
transient channel overload but also causes low-frequency ripple
distortion. The low-frequency ripple distortion can be improved with
the slow recovery time. If different attack times are implemented in
corresponding frequency spectrums in a split band audio system,
high quality performance can be achieved. The buffer amplifier is
designed to make this feature available with minimum external
components. Referring to Figure 6, the rectifier output current is
mirrored into the input and output of the unipolar buffer amplifier A
3
through Q
8
, Q
9
and Q
10
. Diodes D
11
and D
12
improve tracking
accuracy and provide common-mode bias for A
3
. For a
positive-going input signal, the buffer amplifier acts like a
voltage-follower. Therefore, the output impedance of A
3
makes the
contribution of capacitor CR to attack time insignificant. Neglecting
diode impedance, the gain Ga(t) for
G can be expressed as
follows:
Ga(t)
(Ga
INT
Ga
FNL
e
t
A
Ga
FNL
Ga
INT
=Initial Gain
Ga
FNL
=Final Gain
τ
A
=R
A
CA=10k
CA
where
τ
A
is the attack time constant and R
A
is a 10k internal
resistor. Diode D
15
opens the feedback loop of A
3
for a
negative-going signal if the value of capacitor CR is larger than
capacitor CA. The recovery time depends only on CR
R
R
. If the
diode impedance is assumed negligible, the dynamic gain G
R
(t) for
G is expressed as follows.
G
R
(t)
(G
RINT
G
RFNL
e
t
R
G
RFNL
G
R
(t)=(G
R INT
–G
R FNL
) e +G
R FNL
τ
R=R
R
CR=10k
CR
where
τ
R is the recovery time constant and R
R
is a 10k internal
resistor. The gain control current is mirrored to the gain cell through
Q
14
. The low level gain errors due to input bias current of A
2
and A
3
can be trimmed through the tracking trim pin into A
3
with a current
source of
±
3
μ
A.