參數(shù)資料
型號(hào): SA571DR2
廠商: ON Semiconductor
文件頁(yè)數(shù): 6/11頁(yè)
文件大小: 0K
描述: IC COMPANDOR DUAL GAIN 16-SOIC
產(chǎn)品變化通告: Product Obsolescence 11/Feb/2009
標(biāo)準(zhǔn)包裝: 1,000
類型: 壓縮擴(kuò)展器
應(yīng)用: 蜂窩式無(wú)線電,播放器
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
SA571
http://onsemi.com
4
Circuit Description
The SA571 compandor building blocks, as shown in the
block diagram, are a fullwave rectifier, a variable gain cell,
an operational amplifier and a bias system. The arrangement
of these blocks in the IC result in a circuit which can perform
well with few external components, yet can be adapted to
many diverse applications.
The fullwave rectifier rectifies the input current which
flows from the rectifier input, to an internal summing node
which is biased at VREF. The rectified current is averaged on
an external filter capacitor tied to the CRECT terminal, and
the average value of the input current controls the gain of the
variable gain cell. The gain will thus be proportional to the
average value of the input signal for capacitivelycoupled
voltage inputs as shown in the following equation. Note that
for capacitivelycoupled inputs there is no offset voltage
capable of producing a gain error. The only error will come
from the bias current of the rectifier (supplied internally)
which is less than 0.1
mA.
G
T
|V
IN * VREF |avg
R
1
or
G
T
|V
IN |avg
R
1
The speed with which gain changes to follow changes in
input signal levels is determined by the rectifier filter
capacitor. A small capacitor will yield rapid response but
will not fully filter low frequency signals. Any ripple on the
gain control signal will modulate the signal passing through
the variable gain cell. In an expander or compressor
application, this would lead to third harmonic distortion, so
there is a tradeoff to be made between fast attack and decay
times and distortion. For step changes in amplitude, the
change in gain with time is shown by this equation.
t + 10kW
C
RECT
G(t)
+ (G
initial * Gfinal)e
*t
t
) G
final
The variable gain cell is a currentin, currentout device
with the ratio IOUT/IIN controlled by the rectifier. IIN is the
current which flows from the
DG input to an internal
summing node biased at VREF. The following equation
applies for capacitivelycoupled inputs. The output current,
IOUT, is fed to the summing node of the op amp.
I
IN +
V
IN * VREF
R
2
+
V
IN
R
2
A compensation scheme built into the
DG cell
compensates for temperature and cancels out odd harmonic
distortion. The only distortion which remains is even
harmonics, and they exist only because of internal offset
voltages. The THD trim terminal provides a means for
nulling the internal offsets for low distortion operation.
The
operational
amplifier
(which
is
internally
compensated) has the noninverting input tied to VREF, and
the inverting input connected to the
DG cell output as well
as brought out externally. A resistor, R3, is brought out from
the summing node and allows compressor or expander gain
to be determined only by internal components.
The output stage is capable of
± 20 mA output current.
This allows a +13 dBm (3.5 VRMS) output into a 300 W load
which, with a series resistor and proper transformer, can
result in +13 dBm with a 600
W output impedance.
A bandgap reference provides the reference voltage for all
summing nodes, a regulated supply voltage for the rectifier
and
DG cell, and a bias current for the DG cell. The low
tempco of this type of reference provides very stable biasing
over a wide temperature range.
The typical performance characteristics illustration
shows the basic inputoutput transfer curve for basic
compressor or expander circuits.
+20
+10
0
10
20
30
40
50
60
70
80
40
30 20 10
0
+10
COMPRESSOR OUTPUT LEVEL
OR
EXPANDOR INPUT LEVEL (dBm)
COMPRESSOR
INPUT
LEVEL
OR
EXP
ANDOR
Figure 2. Basic InputOutput Transfer Curve
OUTPUT
LEVEL
(dBm)
13
3, 14
2, 15
4
1, 16
200pF
Figure 3. Typical Test Circuit
V1
V2
VO
VCC = 15V
VREF
DG
10
mF
0.1
mF
2.2
mF
2.2
mF
20k
W
10k
2.2
mF
5, 12
8.2k
W
8, 9
30k
W
20k
W
6, 11
7, 10
+
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