參數(shù)資料
型號(hào): SA5214
廠商: NXP Semiconductors N.V.
英文描述: Postamplifier with link status indicator
中文描述: 后置連接狀態(tài)指示燈與
文件頁(yè)數(shù): 3/10頁(yè)
文件大?。?/td> 83K
代理商: SA5214
Philips Semiconductors
Product specification
SA5214
Postamplifier with link status indicator
1998 Oct 07
3
PIN DESCRIPTIONS
PIN
NO.
1
LED
SYMBOL
DESCRIPTION
Output for the LED driver. Open collector output transistor with 125
series limiting resistor. An above threshold signal
turns this transistor ON.
Capacitor for the peak detector. The value of this capacitor determines the detector response time to the signal,
supplementing the internal 10pF capacitor.
Peak detector threshold resistor. The value of this resistor determines the threshold level of the peak detector.
Device analog ground pin.
Peak detector digital output. When this output is LOW, there is data present above the threshold. This pin is normally
connected to the JAM pin and has a TTL fanout of two.
Input to inhibit data flow. Sending the pin HIGH forces TTL DATA OUT ON, Pin 10, LOW. This pin is normally connected
to the FLAG pin and is TTL-compatible.
Power supply pin for the digital portion of the chip.
Power supply pin for the analog portion of the chip.
Device digital ground pin.
TTL output pin with a fanout of five.
Peak detector current resistor. The value of this resistor determines the amount of discharge current available to the
peak detector capacitor, C
PKDET
.
Peak detector hysteresis resistor. The value of this resistor determines the amount of hysteresis in the peak detector.
Non-inverting input to amplifier A2.
Non-inverting output of amplifier A1.
Inverting input to amplifier A2.
Inverting output of amplifier A1.
Auto-Zero capacitor pin (Negative terminal). The value of this capacitor determines the low-end frequency response of
the preamp A1.
Auto-Zero capacitor pin (Positive terminal). The value of this capacitor determines the low-end frequency response of the
preamp A1.
Non-inverting input of the preamp A1.
Inverting input of the preamp A1.
2
C
PKDET
3
4
5
THRESH
GND
A
FLAG
6
JAM
7
8
9
10
11
V
CCD
V
CCA
GND
D
V
OUT
R
PKDET
12
13
14
15
16
17
R
HYST
IN
2A
OUT
1A
IN
2B
OUT
1B
C
AZN
18
C
AZP
19
20
IN
1A
IN
1B
BLOCK DIAGRAM
R
PKDET
20
19
18
17
16 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A1
A2
A3
A4
A5
A6
A7
GATED AMP
OUTPUT BUFFER
OUTPUT DISABLE
PEAK DETECT
LED DRIVER
HYSTERESIS
V
CCA
V
CCD
OUT
1A
OUT
1B
A8
IN
2B
IN
2A
V
OUT
JAM
FLAG
LED
IN
1B
IN
1A
C
AZP
C
AZN
GND
A
GND
D
THRESH
C
PKDET
R
HYST
SD00350
Figure 2. Block Diagram
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