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參數(shù)資料
| 型號： | SA5212AN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Transimpedance amplifier 140MHz |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 186K |
| 代理商： | SA5212AN |
Philips Semiconductors
Product specification
SA5212A
Transimpedance amplifier (140MHz)
1998 Oct 07
4
AC ELECTRICAL CHARACTERISTICS
Minimum and Maximum limits apply over operating temperature range at V
CC
=5V, unless otherwise specified. Typical data applies at V
CC
=5V
and T
A
=25
°
C
5
.
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
R
T
Transresistance (differential output)
DC tested, R
L
=
∞
Test Circuit 6, Procedure 1
DC tested
DC tested, R
L
=
∞
DC tested
Test Circuit 1
D package,
T
A
= 25
°
C
N, FE packages,
T
A
= 25
°
C
9.0
14
19
k
R
O
R
T
R
O
Output resistance (differential output)
Transresistance (single-ended output)
Output resistance (single-ended output)
14
4.5
7
30
7
15
46
9.5
23
k
f
3dB
Bandwidth (-3dB)
100
140
MHz
100
70
120
110
10
9.6
R
IN
C
IN
R/
V
Input resistance
Input capacitance
Transresistance power supply sensitivity
Transresistance ambient
temperature sensitivity
RMS noise current spectral density
(referred to input)
150
18
pF
%/V
V
CC
= 5
±
0.5V
D package
T
A
= T
A MAX
-T
A MIN
Test Circuit 2
f = 10MHz T
A
= 25
°
C
T
A
= 25
°
C Test Circuit 2
f = 50MHz
f = 100MHz
f = 200MHz
f = 50MHz
f = 100MHz
f = 200MHz
Any package
DC tested
V
CC
= 0.1V
Equivalent AC
Test Circuit 3
Any package
f = 0.1MHz
1
Test Circuit 4
R
L
=
∞
Test Circuit 6, Procedure 3
R/
T
0.05
%/
°
C
I
N
2.5
pA/
√
Hz
Integrated RMS noise current over the band-
width (referred to input) C
S
= 0
1
20
27
40
22
32
52
I
T
nA
C
S
= 1pF
PSRR
Power supply rejection ratio
2
20
33
dB
PSRR
Power supply rejection ratio
2
(ECL configuration)
23
dB
V
O MAX
Maximum differential output voltage swing
1.7
3.2
V
P-P
V
IN MAX
Maximum input amplitude for output duty
cycle of 50
±
5%
3
Rise time for 50mV output signal
4
Test Circuit 5
325
mV
P-P
t
R
Test Circuit 5
2.0
ns
NOTES:
1. Package parasitic capacitance amounts to about 0.2pF.
2. PSRR is output referenced and is circuit board layout dependent at higher frequencies. For best performance use RF filter in V
CC
line.
3. Guaranteed by linearity and over load tests.
4. t
R
defined as 20-80% rise time. It is guaranteed by -3dB bandwidth test.
5. As in all high frequency circuits, a supply bypass capacitor should be located as close to the part as possible.
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