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參數(shù)資料
| 型號： | SA5090N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 外設及接口 |
| 英文描述： | Addressable relay driver |
| 中文描述： | 0.15 A ADDR LATCH BASED PRPHL DRVR, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 93K |
| 代理商： | SA5090N |
Philips Semiconductors Linear Products
Product specification
NE/SA5090
Addressable relay driver
512
August 31, 1994
853-0892 13721
DESCRIPTION
The NE/SA5090 addressable relay driver is a high-current latched
driver, similar in function to the 9934 address decoder. The device
has 8 open-collector Darlington power outputs, each capable of
150mA load current. The outputs are turned on or off by respectively
loading a logic “1” or logic “0” into the device data input. The
required output is defined by a 3-bit address. The device must be
enabled by a CE input line which also serves the function of further
address decoding. A common clear input, CLR, turns all outputs off
when a logic “0” is applied. The device is packaged in a 16-pin
plastic or Cerdip package.
FEATURES
8 high-current outputs
Low-loading bus-compatible inputs
Power-on clear ensures safe operation
Will operate in addressable or demultiplex mode
Allows random (addressed) data entry
Easily expandable
Pin-compatible with 9334 (Siliconix or Fairchild)
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
D
1
, N Packages
TOP VIEW
NOTE:
1. SOL - Released in Large SO package only.
A
0
A
1
A
2
Q
0
Q
1
Q
2
Q
3
GND
V
CC
CLR
CE
D
Q
7
Q
6
Q
5
Q
4
APPLICATIONS
Relay driver
Indicator lamp driver
Triac trigger
LED display digit driver
Stepper motor driver
BLOCK DIAGRAM
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
CLR
CE
A
0
A
1
A
2
D
1–OF–8
DECODER
CONTROL
GATE
V
CC
OUTPUT STAGE
INPUT STAGE
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
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