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參數(shù)資料
| 型號(hào)： | SA25C512LEN |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DUCT CORNER STRIP PVC LT GY 3H |
| 中文描述： | 512KB的EEPROM中具有10MHz的SPI和低待機(jī) |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大?。?/td> | 1078K |
| 代理商： | SA25C512LEN |
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SA25C512 Data Sheet
SAIFUN
12
Table 9. Read Status Register Definition
Bit
Definition
Bit 0 (/RDY)
Bit 0 = 0 (/RDY) indicates that the
device is READY.
Bit 0 = 1 indicates that a write cycle
is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates that the device is
not write enabled.
Bit 1 = 1 indicates that the device is
write enabled.
Bit 2 (BP0)
Block Write Protect Bit 0
Bit 3 (BP1)
Block Write Protect Bit 1
Bit 7
(WPBEN)
Write Protect Mode Enable Bit
Bits 4-6 are 0s when the device is not in an internal
write cycle; bits 0-7 are 1s during an internal write
cycle.
Write Sequence (WRITE)
Two
executed in order to write to the
SA25C512. The device must first be write
enabled via the WREN instruction, and
then
a
WRITE
instruction
executed. The address of the memory
locations to be written must be outside the
protected address field location selected by
the Block Write Protection level. During an
internal write cycle, all commands are
ignored except the RDSR instruction.
separate
instructions
must
be
may
be
A WRITE instruction requires the following
sequence:
1. After the CSb line is pulled low to select
the device, the WRITE opcode is
transmitted via the SI line, followed by
the byte address and the data (D7-D0)
to be written.
2. Programming starts after the CSb pin is
brought high. The CSb pin's low-to-high
transition must occur during the SCK
low time, immediately after clock in the
D0 (LSB) data bit.
The SA25C512 is capable of up to a
128-byte (from 1 to 128 bytes) PAGE write
operation. After each byte is received, the
eight low-order address bits are internally
incremented by one. If more than 128
bytes of data are transmitted, the address
counter rolls over and the previously
written data is overwritten. The SA25C512
is automatically returned to the write
disable state at the completion of a write
cycle.
NOTE:
If the device is not write enabled, the
device ignores the WRITE instruction
and returns to the standby state when
CSb is brought high. A new CSb falling
edge is required to re-initiate the serial
communication.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SA25C512LMN | DUCT CORNER STRIP PVC LT GY 4H |
| SA25C512LN | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA25C512HEMNX | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA25C512HEN | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SA25C512HENX | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SA25C512LENX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
| SA25C512LMN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
| SA25C512LMNX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
| SA25C512LN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
| SA25C512LNX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:512Kb EEPROM SPI with 10MHz and Low Standby |
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