參數(shù)資料
型號: SA25C512HNX
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內256個8位每字舉辦的串行CMOS
文件頁數(shù): 2/19頁
文件大小: 1078K
代理商: SA25C512HNX
SA25C512 Data Sheet
SAIFUN
2
Table of Contents
Features......................................................................... 1
General Description...................................................... 1
Ordering Information .................................................... 5
Product Specifications ................................................. 6
Absolute Maximum Ratings..................................... 6
Latch Up Specifications........................................... 6
ESD Specifications.................................................. 6
Operating Conditions............................................... 6
DC Characteristics........................................................ 7
AC Test Conditions....................................................... 8
Serial Interface Description.......................................... 9
Master..................................................................... 9
Slave....................................................................... 9
Transmitter/Receiver............................................... 9
Serial Opcode ......................................................... 9
Invalid Opcode ........................................................ 9
Chip Select (CSb).................................................... 9
HOLDb.................................................................... 9
Write Protect........................................................... 9
Functional Description ............................................... 10
Write Enable (WREN)........................................... 10
Write Disable (WRDI)............................................ 10
Read Status Register (RDSR)............................... 11
Write Status Register (WRSR).............................. 11
Read Sequence (READ) ....................................... 11
Write Sequence (WRITE)...................................... 12
Timing Diagrams......................................................... 13
Physical Dimensions .................................................. 16
Life Support Policy...................................................... 19
List of Figures
Figure 1. SOIC 8 – Narrow/PDIP Package (Top View)....4
Figure 2: SA25C512 Ordering Information ......................5
Figure 3. AC Measurements I/O Waveform.....................8
Figure 4. SPI Serial Interface ........................................ 10
Figure 5. SPI Mode 0 (0,0) Timing................................. 13
Figure 6. SPI Mode 0 (0,0) and 3 (1,1) Timing............... 13
Figure 7. HOLDb Timing ............................................... 14
Figure 8. Read Timing................................................... 14
Figure 9. Write Timing................................................... 14
Figure 10. Write Status Register Timing........................ 15
Figure 11. Read Status Register Timing........................ 15
Figure 12. 8-pin SOIC Package..................................... 16
Figure 13. 8-pin Molded Small Outline Package (MN),
0.150” Wide Body, JEDEC SOIC......................... 17
Figure 14. Molded Dual-in-line Package (N) Package
Number N08E...................................................... 18
List of Tables
Table 1. Pin Names.........................................................4
Table 2. DC Characteristics.............................................7
Table 3. AC Measurements.............................................8
Table 4. AC Characteristics.............................................8
Table 5. Instruction Set ................................................. 10
Table 6. Status Register Format.................................... 10
Table 7. Block Write Protect Bits................................... 11
Table 8. WPBEN Operation .......................................... 11
Table 9. Read Status Register Definition....................... 12
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