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型號(hào)：	S9S12XS256J0VAER
廠商：	Freescale Semiconductor
文件頁(yè)數(shù)：	123/738頁(yè)
文件大?。?/td>	0K
描述：	MCU 16BIT 256K FLASH 64LQFP
標(biāo)準(zhǔn)包裝：	1,500
系列：	HCS12X
核心處理器：	HCS12X
芯體尺寸：	16-位
速度：	40MHz
連通性：	CAN，SCI，SPI
外圍設(shè)備：	LVD，POR，PWM，WDT
輸入/輸出數(shù)：	44
程序存儲(chǔ)器容量：	256KB（256K x 8）
程序存儲(chǔ)器類型：	閃存
RAM 容量：	12K x 8
電壓 - 電源 (Vcc/Vdd)：	1.72 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器：	A/D 8x12b
振蕩器型：	外部
工作溫度：	-40°C ~ 105°C
封裝/外殼：	64-LQFP
包裝：	帶卷 (TR)

S12X Debug (S12XDBGV3) Module

S12XS Family Reference Manual Rev. 1.13

Freescale Semiconductor

The trigger priorities described in Table 6-39 dictate that in the case of simultaneous matches, the match

on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to

final state has priority over all other matches.

6.3.2.7.4

Debug Match Flag Register (DBGMFR)

Read: If COMRV[1:0] = 11

Write: Never

DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four ag bits each mapped directly

to a channel. Should a match occur on the channel during the debug session, then the corresponding ag

is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents

are retained after a debug session for evaluation purposes. These ags cannot be cleared by software, they

are cleared only when arming the module. A set ag does not inhibit the setting of other ags. Once a ag

is set, further triggers on the same channel have no affect.

Comparator Register Descriptions

Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG

module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare

registers, two data bus compare registers, two data bus mask registers and a control register).

Any match triggers to Final State

Match0 triggers to State1....... Other matches have no effect

Match0 triggers to State2....... Other matches have no effect

Match0 triggers to Final State.......Match1 triggers to State1...Other matches have no effect

Match1 triggers to State1....... Other matches have no effect

Match1 triggers to State2....... Other matches have no effect

Match1 triggers to Final State....... Other matches have no effect

Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect

Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect

Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect

Match2 triggers to Final State....... Other matches have no effect

Match3 triggers to Final State....... Other matches have no effect

Reserved. (No match triggers state sequencer transition)

Reserved. (No match triggers state sequencer transition)

Address: 0x0027

= Unimplemented or Reserved

Figure 6-12. Debug Match Flag Register (DBGMFR)

Table 6-24. State3 — Sequencer Next State Selection

Description

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S9S12XS256J0VAL	制造商:Freescale Semiconductor 功能描述:
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S9S12XS256J1CAA	制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12 Microcontrollers
S9S12XS256J1CAAR	制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12 Microcontrollers
S9S12XS256J1CAE	制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12 Microcontrollers

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