參數(shù)資料
型號(hào): S9737-03
廠商: Hamamatsu Photonics
英文描述: CCD area image sensor 1024 】 1024 pixels, front-illuminated FFT-CCDs
中文描述: 防治荒漠化領(lǐng)域的圖像傳感器1024】1024像素,前照明的傅里葉變換的CCD
文件頁數(shù): 4/9頁
文件大?。?/td> 799K
代理商: S9737-03
CCD area image sensor
S9737 series
4
I
Pin connections (S9737-02)
Pin No.
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TSH1
16
TSC1
17
TSC2
18
19
20
21
22
23
24
25
26
27
28
TSH2
Description
Remark
P-
NC
SS
NC
ISV
IG2V
IG1V
RG
RD
OS
OD
OG
SG
P+
TE-cooler-
Substrate (GND)
Test point (vertical input source)
Test point (vertical input gate-2)
Test point (vertical input gate-1)
Reset gate
Reset drain
Output transistor source
Output transistor drain
Output gate
Summing gate
TE-cooler+
Temperature sensor (hot side)
Temperature sensor (cool side)
Temperature sensor (cool side)
CCD horizontal register clock-2
CCD horizontal register clock-1
Test point (horizontal input gate-2)
Test point (horizontal input gate-1)
Test point (horizontal input source)
CCD vertical register clock-2
CCD vertical register clock-1
Transfer gate
Shorted to RD
Shorted to 0 V
Shorted to 0 V
Same timing as P2H
P2H
P1H
IG2H
IG1H
ISH
P2V
P1V
TG
NC
NC
Shorted to 0 V
Shorted to 0 V
Shorted to RD
Same timing as P2V *
12
Temperature sensor (hot side)
I
Pad connections (S9737-03)
Pad No.
Symbol
1
2
3
4
5
6
7
8
9
10
11
IG2H
12
IG1H
13
14
15
16
17
18
19
20
21
22
23
IG2V
24
IG1V
*12: TG is an isolation gate between vertical register and horizontal register.
In standard operation, the same pulse of P2V should be applied to the TG.
Description
Remark
RG
RD
OS
OD
OG
SG
NC
NC
P2H
P1H
Reset gate
Reset drain
Output transistor source
Output transistor grain
Output gate
Summing gate
CCD horizontal register clock-2
CCD horizontal register clock-1
Test point (horizontal input gate-2)
Test point (horizontal input gate-1)
Test point (horizontal input source)
CCD vertical resister clock-2
CCD vertical resister clock-1
Transfer gate
ISH
P2V
P1V
TG
NC
NC
NC
SS
NC
ISV
Same timing as P2V*
12
Substrate (GND)
Test point (vertical input source)
Test point (vertical input gate-2)
Test point (vertical input gate-1)
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