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參數(shù)資料
| 型號： | S9418 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad 8-Bit Nonvolatile DACPOT⑩ Electronic Potentiometer With a Mute Control Input |
| 中文描述： | 四8位非易失DACPOT⑩電子電位隨著靜音控制輸入 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 50K |
| 代理商： | S9418 |
2
S9418
2023 1.5 4/24/99
The analog outputs of the S9418 can be programmed to
any one of 256 individual voltage steps. Each step value
is 1/256
th
of the voltage differential between VrefH and
VrefL of the respective DAC. Once programmed these
settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read
cycle. In addition each output can be adjusted an unlim-
ited number of times without altering the value stored in
the nonvolatile memory.
DEVICE OPERATION
Analog Section
The S9418 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.
Reference inputs
The voltage differential between the V
REFL
and V
REFH
inputs sets the full-scale output voltage for its respective
DAC. V
REFL
must be equal to or greater than ground
(positive voltage). V
REFH
must be greater (more positive)
than V
REFL
or equal to V
DD
.
PINOUT and SIGNAL DEFINITION
Pin
Name
Function
20, 19
V
REFH
Vreference High:
V
REFH
≤
V
DD
> V
REFL
3
V
DD
Power Supply Voltage
4
RDY/
BSY
Ready/Busy: open drain output
indicating status of nonvolatile
write operations
5
CLK
Clock Input Pin: used for serial
data communication
6
CS
Chip Select: When high deselects
the device and places it in a low
power mode
7
DI
Data Input: serial data input pin
8
DO
Data Output: serial data output pin
9
MUTE
When active forces V
OUT
to V
REFL
10
GND
Power Supply Ground
11, 12
13, 14
V
REFL
Vreference Low
15, 16
17, 18
V
OUT
DAC Output: buffered D to A
converter output
Output Buffer Amplifiers
The voltage outputs are from precision unity-gain follow-
ers that can slew up to 1V/
μ
s. The outputs can swing from
V
REFL
to V
REFH
. With a 0V to 5V output transition the
amplifier outputs typically settle to 1LSB in 50
μ
s.
DIGITAL INTERFACE
The S9418 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (
CS
) and Data
In (DI) input and a Data Out (DO) output. Data is clocked
into the device on the clock’s rising edge and out of the
device on the clock’s falling edge. Data is shifted in and
out MSB first. DO only becomes active after the device
has been selected and after a valid read command and
address has been received.
All data transfers are initiated after
CS
goes LOW and a
logic ‘1’ is clocked into the device. This first data transfer
is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.
1
2
3
4
5
6
7
8
9
10
V
REFH
1
V
REFH
0
V
DD
CLK
RDY/BSY
CS
DI
DO
GND
11
12
13
14
15
16
17
18
19
20
V
REFH
2
V
REFH
3
V
OUT
0
V
OUT
1
V
OUT
2
V
OUT
3
V
REFL
3
V
REFL
2
V
REFL
1
V
REFL
0
MUTE
2023 ILL1 1.2
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