參數(shù)資料
型號: S87C654-4
廠商: NXP Semiconductors N.V.
英文描述: 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C
中文描述: 80C51的8位微控制器8K/16K,256檢察官辦公室和I2C
文件頁數(shù): 12/24頁
文件大小: 195K
代理商: S87C654-4
Philips Semiconductors
Product specification
87C652/87C654
80C51 8-bit microcontroller
8K/16K, 256 OTP, I
2
C
1999 Jul 23
12
AC ELECTRICAL CHARACTERISTICS – I
2
C INTERFACE
SYMBOL
PARAMETER
INPUT
OUTPUT
SCL TIMING CHARACTERISTICS
t
HD
; STA
START condition hold time
t
LOW
SCL LOW time
t
HIGH
SCL HIGH time
t
RC
SCL rise time
t
FC
SCL fall time
SDA TIMING CHARACTERISTICS
t
SU
; DAT1
Data set-up time
t
SU
; DAT2
SDA set-up time (before rep. START cond.)
t
SU
; DAT3
SDA set-up time (before STOP cond.)
t
HD
; DAT
Data hold time
t
SU
; STA
Repeated START set-up time
t
SU
; STO
STOP condition set-up time
t
BUF
Bus free time
t
RD
SDA rise time
t
FD
SDA fall time
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1
μ
s.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t
CLCL
will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. t
CLCL
= 1/f
OSC
= one oscillator clock period at pin XTAL1. For 62 ns < t
CLCL
< 285 ns (16 MHz) > f
OSC
> 3.5 MHz) the SI01 interface meets
the I
2
C-bus specification for bit-rates up to 100 kbit/s.
14 t
CLCL
16 t
CLCL
14 t
CLCL
1
μ
s
0.3
μ
s
> 4.0
μ
s
1
> 4.7
μ
s
1
> 4.0
μ
s
1
2
< 0.3
μ
s
3
250 ns
250 ns
250 ns
0 ns
14 t
CLCL
14 t
CLCL
14 t
CLCL
1
μ
s
0.3
μ
s
> 20 t
CLCL
– t
RD
> 1
μ
s
1
> 8 t
CLCL
> 8 t
CLCL
– t
FC
> 4.7
μ
s
1
> 4.0
μ
s
1
> 4.7
μ
s
1
2
< 0.3
μ
s
3
TIMING SIO1 (I
2
C) INTERFACE
t
RD
t
SU;STA
t
BUF
t
SU;STO
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
FD
t
RC
t
FC
t
HIGH
t
LOW
t
HD;STA
t
SU;DAT1
t
HD;DAT
t
SU;DAT2
t
SU;DAT3
START condition
repeated START condition
SDA
(INPUT/OUTPUT)
SCL
(INPUT/OUTPUT)
STOP condition
START or repeated START condition
SU00107A
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