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參數(shù)資料
| 型號： | S87C652-5F40 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS single-chip 8-bit microcontrollers |
| 中文描述： | 8-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 185K |
| 代理商： | S87C652-5F40 |
Phlips Semiconductors
Product specification
80C652/83C652
CMOS single-chip 8-bit microcontrollers
1997 Dec 05
6
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
DIP
PLCC
QFP
TYPE
NAME AND FUNCTION
V
SS
20
22
6, 16,
28, 39
I
Ground:
0V reference. With the QFP package all V
SS
pins (V
SS1
to V
SS4
) must be
connected.
V
DD
40
44
38
I
Power Supply:
This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32
43–36
37–30
I/O
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
which are open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:
I
IL
). Alternate functions include:
SCL:
I
2
C-bus serial port clock line.
SDA:
I
2
C-bus serial port data line.
P1.6
P1.7
7
8
8
9
2
3
I/O
I/O
P2.0–P2.7
21–28
24–31
18–25
I/O
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features of
the 80C51 family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
RST
9
10
4
I
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an external
capacitor to V
DD
.
Address Latch Enable:
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency. Note that one ALE pulse is skipped during each access to external
data memory.
ALE
30
33
27
I/O
PSEN
29
32
26
O
Program Store Enable:
Read strobe to external program memory via Port 0 and Port 2. It
is activated twice each machine cycle during fetches from the external program memory.
When executing out of external program memory two activations of PSEN are skipped
during each access to external data memory. PSEN is not activated (remains HIGH) during
no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can
drive CMOS inputs without external pull–ups.
EA
31
35
29
I
External Access:
If during a RESET, EA is held at TTL, level HIGH, the CPU executes out
of the internal program memory ROM provided the Program Counter is less than 8192. If
during a RESET, EA is held a TTL LOW level, the CPU executes out of external program
memory. EA is not allowed to float.
XTAL1
19
21
15
I
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
NOTE:
To avoid “l(fā)atch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
DD
+ 0.5V or V
SS
– 0.5V, respectively.
18
20
14
O
Crystal 2:
Output from the inverting oscillator amplifier.
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