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參數(shù)資料
| 型號(hào)： | S83C654IFPN |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | CMOS single-chip 8-bit microcontroller |
| 中文描述： | CMOS單芯片8位微控制器 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 480K |
| 代理商： | S83C654IFPN |
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Philips Semiconductors
Product specification
87C654
CMOS single-chip 8-bit microcontroller
1996 Aug 16
14
AC ELECTRICAL CHARACTERISTICS
1, 2
20MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
2
Oscillator frequency:
Speed Versions
87C654
–7, –8
3.5
20
MHz
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
2
ALE pulse width
60
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
ns
2
Address valid to ALE low
25
ns
2
Address hold after ALE low
25
ns
2
ALE low to valid instruction in
135
4t
CLCL
–65
ns
2
ALE low to PSEN low
25
t
CLCL
–25
3t
CLCL
–45
ns
2
PSEN pulse width
105
ns
2
PSEN low to valid instruction in
90
3t
CLCL
–60
ns
2
Input instruction hold after PSEN
0
0
ns
2
Input instruction float after PSEN
25
t
CLCL
–25
5t
CLCL
–80
10
ns
2
Address to valid instruction in
170
ns
2
PSEN low to address float
10
ns
t
AVLL
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
DW
t
WHQX
t
RLAZ
t
WHLH
Shift Register
3, 4
Address valid to ALE low
25
t
CLCL
–25
6t
CLCL
–100
6t
CLCL
–100
ns
3, 4
RD pulse width
200
ns
3, 4
WR pulse width
200
ns
3, 4
RD low to valid data in
160
5t
CLCL
–90
ns
3, 4
Data hold after RD
0
0
ns
3, 4
Data float after RD
72
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
ns
3, 4
ALE low to valid data in
250
ns
3, 4
Address to valid data in
285
ns
3, 4
ALE low to RD or WR low
100
200
3t
CLCL
–50
4t
CLCL
–75
t
CLCL
–30
7t
CLCL
–130
t
CLCL
–25
ns
3, 4
Address valid to WR low or RD low
125
ns
3, 4
Data valid to WR transition
20
ns
3, 4
Data setup time before WR
220
ns
3, 4
Data hold after WR
25
ns
3, 4
RD low to address float
0
0
ns
3, 4
RD or WR high to ALE high
25
75
t
CLCL
–25
t
CLCL
+25
ns
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
External Clock
5
Serial port clock cycle time
3
Output data setup to clock rising edge
3
Output data hold after clock rising edge
3
Input data hold after clock rising edge
3
Clock rising edge to input data valid
3
0.6
12t
CLCL
10t
CLCL
–133
2t
CLCL
–60
0
μ
s
ns
5
367
5
40
ns
5
0
ns
5
367
10t
CLCL
–133
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
6
High time
3
Low time
3
Rise time
3
Fall time
3
17
17
t
CLCL –
t
LOW
t
CLCL –
t
HIGH
20
ns
6
17
17
ns
6
20
ns
6
20
20
ns
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| S83C751-1A28 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count |
| S83C751-1DB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count |
| S83C751-1N24 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count |
| S83C751-2A28 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count |
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