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參數(shù)資料
| 型號： | S8301 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | HD-SDI(High Definition Serial Digital Interface) Data Retimer(高分辨率串行數(shù)字接口重定時器) |
| 中文描述： | HD - SDI信號（高清晰度串行數(shù)字接口）數(shù)據(jù)重定時器（高分辨率串行數(shù)字接口重定時器） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 115K |
| 代理商： | S8301 |
2
HD-SDI DATA RETIMER
S8301
December 8, 1998 / Revision A
OVERVIEW
The Data Retimer performs two functions. The first is to
perform the function of a Port Bypass Circuit for nodes
in a multi-rate switch or router. The low jitter accumula-
tion of the Port Bypass Path is essential in these sys-
tems. The second function is to retime and restore
signal quality after transmission and equalization. The
low jitter transfer peaking and the high jitter tolerance
specifications of the Clock and Data Recovery PLL are
essential in these applications. In addition, the Lock
detect circuit monitors the incoming signals for run
length, transition density and frequency. The output of
this circuit is useful for link performance monitoring and
detection of channel present.
JITTER PERFORMANCE
The Data Retimer complies with the minimum jitter tol-
erance requirements proposed by SMPTE 292M when
used with differential inputs and outputs. In addition, the
Data Retimer is designed for minimum jitter generation
and jitter transfer specifications. This allows the opti-
mum system design for arbitrated loop architectures.
Jitter Tolerance
Input jitter tolerance is defined as the amplitude of
frequency dependent, random and deterministic jitter
that causes the clock recovery PLL to violate the
BER specifications.
Alignment Jitter
The variation in position of a signal's transitions rela-
tive to those of a clock extracted from that signal. The
bandwidth of the clock extraction process determines
the low-frequency limit for alignment jitter. Alignment
jitter is out of band with respect to the PLL bandwidth.
Timing Jitter
The variation in a position of a signal's transitions
occuring at a rate greater than a specified frequency,
typically 10 Hz. Variations occuring below this speci-
fied frequency are termed wander and are not ad-
dressed by this practice. Timing jitter is in band with
respect to the PLL bandwidth.
Deterministic Jitter Tolerance
Deterministic Jitter Tolerance is the amount of Deter-
ministic jitter that the clock recovery PLL must tolerate.
Lock Detect
The Data Retimer lock detect circuit monitors the
selected input signal to detect the presence of the
channel. This is done by monitoring the run length,
transition density and frequency content of the in-
coming data. The frequency monitor circuit checks
the difference between the divided down recovered
clock and the externally supplied reference clock
(REFCLK). If the frequency difference of the recov-
ered clock and the reference clock varies by more
than
±
240 ppm the part will be declared out of lock.
In the out of lock state the PLL will lock to the local
reference clock and periodically poll the serial data
inputs looking for data with valid frequency content.
The lock detect output transitions to a logic 1 when
the PLL is locked to data, and transitions to a logic 0
when locked to the reference clock.
VALID DATA
DATAP/N or
ALTP/N
LOCKDET
Figure 3. LOCKDET Function
Figure 2. Functional Block Diagram
Phase
Detect
Loop
Filter
Freq
Detect
Run
Length
Detect
Divide
by 20
VCO
REFCLK
ALTP/N
SEL
DATAP/N
LOCKDET
DOUTP/N
BPSSP/N
HDTV Clock and Data Retimer
D Q
M
U
X
CK
LOCK2REF
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