
Rev.3.2
_10
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Electrical Characteristics
Seiko Instruments Inc.
7
Table 6 (1 / 2)
(Ta
=
25
°
C unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Measure-
ment
condition
Measure-
ment
circuit
Detection voltage
Over charge detection voltage1
Over charge release voltage1
Over discharge detection voltage1
Over discharge release voltage1
Over charge detection voltage 2
Over charge release voltage 2
Over discharge detection voltage 2
Over discharge release voltage 2
Over charge detection voltage3
Over charge release voltage3
Over discharge detection voltage3
Over discharge release voltage3
Over current detection voltage1
*1
Over current detection voltage 2
Over current detection voltage3
Voltage temperature factor 1
*2
Voltage temperature factor 2
*3
Delay time
Over charge detection delay time1
Over charge detection delay time 2
Over charge detection delay time3
Over discharge detection delay time1
Over discharge detection delay time 2
Over discharge detection delay time3
Over current detection delay time1
Over current detection delay time 2
Over current detection delay time3
Operating voltage
Operating voltage between VCC and
VSS
*4
Current consumption
Current consumption (during normal
operation)
Current consumption for cell 2
Current consumption for cell 3
Current consumption at power down
Internal resistance
Resistance between
VCC and VMP
V
CU1
V
CD1
V
DD1
V
DU1
V
CU2
V
CD2
V
DD2
V
DU2
V
CU3
V
CD3
V
DD3
V
DU3
V
IOV1
V
IOV2
V
IOV3
T
COE1
4.10 to 4.35 Adjustment
3.85 to 4.35 Adjustment
2.00 to 2.70 Adjustment
2.00 to 3.70 Adjustment
4.10 to 4.35 Adjustment
3.85 to 4.35 Adjustment
2.00 to 2.70 Adjustment
2.00 to 3.70 Adjustment
4.10 to 4.35 Adjustment
3.85 to 4.35 Adjustment
2.00 to 2.70 Adjustment
2.00 to 3.70 Adjustment
0.15 to 0.50V Adjustment
V
CC
Reference
V
SS
Reference
Ta=-20 to 70°C
Ta=-20 to 70°C
V
CU1
0.05
V
CD1
0.10
V
DD1
0.08
V
DU1
0.10
V
CU2
0.05
V
CD2
0.10
V
DD2
0.08
V
DU2
0.10
V
CU3
0.05
V
CD3
0.10
V
DD3
0.08
V
DU3
0.10
V
IOV1
x 0.9
0.54
V
CU1
V
CU1
+0.05
V
CD1
V
CD1
+0.10
V
DD1
V
DD1
+0.08
V
DU1
V
DU1
+0.10
V
CU2
V
CU2
+0.05
V
CD2
V
CD2
+0.10
V
DD2
V
DD2
+0.08
V
DU2
V
DU2
+0.10
V
CU3
V
CU3
+0.05
V
CD3
V
CD3
+0.10
V
DD3
V
DD3
+0.08
V
DU3
V
DU3
+0.10
V
IOV1
V
IOV1
x 1.1
0.6
V
1
1
V
1
1
V
1
1
V
1
1
V
2
1
V
2
1
V
2
1
V
2
1
V
3
1
V
3
1
V
3
1
V
3
1
V
4
2
0.66
V
4
2
1.0
1.0
0.5
2.0
3.0
V
4
2
0
1.0
mV/
°
C
mV/
°
C
T
COE2
0
0.5
t
CU1
t
CU2
t
CU3
t
DD1
t
DD2
t
DD3
t
IOV1
t
IOV2
C
CCT
=0.47
μ
F
C
CCT
=0.47
μ
F
C
CCT
=0.47
μ
F
C
CDT
=0.1
μ
F
C
CDT
=0.1
μ
F
C
CDT
=0.1
μ
F
C
COVT
=0.1
μ
F
0.5
1.0
1.5
s
9
6
0.5
1.0
1.5
s
10
6
0.5
1.0
1.5
s
11
6
20
40
60
ms
9
6
20
40
60
ms
10
6
20
40
60
ms
11
6
10
20
30
ms
12
7
2
4
8
ms
μ
s
12
7
t
IOV3
FET gate capacitor =2000 pF
100
300
550
12
7
V
DSOP
2.0
24
V
I
OPE
V1=V2=V3=3.5 V
20
50
μ
A
5
3
I
CELL2
I
CELL3
I
PDN
V1=V2=V3=3.5 V
300
300
0
300
nA
5
3
V1=V2=V3=3.5 V
0
300
nA
μ
A
M
M
M
M
5
3
V1=V2=V3=1.5 V
0.1
5
3
R
VCM
V1=V2=V3=3.5 V
V1=V2=V3=3.5 V
*5
0.40
0.90
1.40
6
3
0.20
0.50
0.80
6
3
R
VSM
V1=V2=V3=1.5 V
V1=V2=V3=1.5 V
*5
0.40
0.90
1.40
6
3
Resistance between
VSS and VMP
Input voltage
CTL"H" Input voltage
0.20
0.50
0.80
6
3
V
CTL(H)
V
CC
x0.8
V
CTL"L" Input voltage
V
CTL(L)
V
CC
x0.2
V