
Rev.1.2
S-818 Series
LOW DROPOUT CMOS VOLTAGE REGULATOR
Seiko Instruments Inc.
7
Operation
1. Basic operation
Figure 7 shows the block diagram of the S-818
Series.
The error amplifier compares a reference voltage
V
REF
with the part of the output voltage divided by the
feedback resistors Rs and Rf. It supplies the output
transistor with the gate voltage, necessary to ensure
certain output voltage free of any fluctuations of input
voltage and temperature.
2. Output transistor
The S-818 Series uses a low on-resistance Pch MOS FET as the output transistor.
Be sure that V
OUT
does not exceed V
IN
+0.3 V to prevent the voltage regulator from being broken due to
inverse current flowing from V
OUT
pin to V
IN
pin through the parasitic diode.
3. Power Off Pin (ON/OFF Pin)
This pin activates and inactivates the regulator.
When the ON/OFF pin is switched to the power off level, the operation of all internal circuit stops, the built-in
Pch MOSFET output transistor between V
IN
and V
OUT
pin is switched off, suppressing current consumption.
The V
OUT
pin goes to the Vss level due to internal divided resistance of several M
between V
OUT
pin and
V
SS
pin.
The structure of the ON/OFF pin is shown in Figure 8. Since the ON/OFF pin is neither pulled down nor pulled
up internally, do not keep it in the floating state. Current consumption increases if a voltage of 0.3 V to V
IN
-0.3
V is applied to the ON/OFF pin. When the power off pin is not used, connect it to the V
IN
pin for product type
"A" and to the V
SS
pin for product type "B".
Table 6 Power off pin function by product type
Product
type
A
A
B
B
ON/OFF pin
Internal
circuit
Operating
Stop
Stop
Operating
VOUT pin
voltage
Set value
V
SS
level
V
SS
level
Set value
Current
consumption
Iss1
Iss2
Iss2
Iss1
“H” : Power on
“L” : Power off
“H” : Power off
“L” : Power on
Reference
voltage
circuit
VOUT
*1
*1 Parasitic diode
VSS
VIN
Rs
Rf
Error amplifier
Current
source
Vref
ON/OFF
VIN
Figure 8 ON/OFF Pin
Figure 7 Typical Circuit Block Diagram