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參數(shù)資料
| 型號(hào)： | S80C52EXXX-30:D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44 |
| 文件頁(yè)數(shù)： | 31/109頁(yè) |
| 文件大?。?/td> | 10824K |
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276
7593L–AVR–09/12
AT90USB64/128
1 - Reserved
The value read from this bits is always 0. Do not set this bit
0 - SUSPE - Suspend Interrupt Enable Bit
Set to enable the SUSPI interrupt.
Clear to disable the SUSPI interrupt.
7 - ADDEN - Address Enable Bit
Set to activate the UADD (USB address).
Cleared by hardware. Clearing by software has no effect.
See Section 23.7, page 264 for more details.
6-0 - UADD6:0 - USB Address Bits
Load by software to configure the device address.
7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
2-0 - FNUM10:8 - Frame Number Upper Value
Set by hardware. These bits are the three MSB of the 11-bits Frame Number information. They
are provided in the last received SOF packet. FNUM is updated if a corrupted SOF is received.
Frame Number Lower Value
Set by hardware. These bits are the eight LSB of the 11-bits Frame Number information.
7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
4 - FNCERR -Frame Number CRC Error flag
Set by hardware when a corrupted Frame Number in start of frame packet is received.
This bit and the SOFI interrupt are updated at the same time.
Bit
7
65432
10
ADDEN
UADD6:0
UDADDR
Read/write
W
R/W
Initial value
0
00000
00
Bit
76543
2
1
0
-----
FNUM10:8
UDFNUMH
Read/write
R
RRR
Initial value
00000
0
Bit
765432
10
FNUM7:0
UDFNUML
Read/write
RR
RRRRRR
Initial value
000000
00
Bit
7
65
43
21
0
-
FNCERR
-
UDMFN
Read/write
R
Initial value
00
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