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參數資料
| 型號： | S80C52EXXX-20SHXXX:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 101/109頁 |
| 文件大?。?/td> | 10824K |
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77
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter
number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines
in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
12.2.1 Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit
registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in
section “Accessing 16-bit Registers” on page 93. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers
and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK). TIFR and TIMSK are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock
Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value.
The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as
the timer clock (clkT1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The
result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the
Output Compare pin (OC1A/B). See “Output Compare Units” on page 80. The compare match event will also set the
Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the
Input Capture pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 105). The Input Capture
unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A
Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A
Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered
allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an
alternative, freeing the OCR1A to be used as PWM output.
12.2.2 Definitions
The following definitions are used extensively throughout the section:
Table 12-1. Definitions
12.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock
Select logic which is controlled by the Clock Select (CS1[2:0]) bits located in the Timer/Counter control Register B
(TCCR1B). For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 103.
Constant
Description
BOTTOM
The counter reaches BOTTOM when it becomes 0x00
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
TOP
The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP
value can be assigned to be the fixed value 0xFF (MAX), the value stored in the OCR
1A register, or the
value stored in the ICR1 register. The assignment depends on the mode of operation
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