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參數(shù)資料
| 型號： | S80C32E-30SHXXX:R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 7/91頁 |
| 文件大?。?/td> | 19688K |
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112
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
13.10.2 Timer/Counter1 Control Register B – TCCR1B
Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the input capture noise canceler. When the noise canceler is activated, the input from the input
capture pin (ICPn) is filtered. The filter function requires four successive equal valued samples of the ICPn pin for changing its
output. The input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled.
Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the input capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written
to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger
the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the input capture register (ICRn).
The event will also set the input capture flag (ICFn), and this can be used to cause an input capture interrupt, if this interrupt is
enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB register),
the ICPn is disconnected and consequently the input capture function is disabled.
Bit 5 – RTGEN
Set this bit to enable the ICP1A as a Timer/Counter retrigger input.
(This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB
is written.)
Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA register description.
Bit 2:0 – CSn2:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 13-10 and Figure 13-11.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is
configured as an output. This feature allows software control of the counting.
Bit
7
6
5
4
3
2
1
0
ICNC1
ICES1
RTGEN
WGM13
WGM12
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R
R/W
Initial Value
0
Table 13-5. Clock Select Bit Description
CSn2
CSn1
CSn0
Description
0
No clock source (Timer/Counter stopped).
0
1
clkI/O/1 (no prescaling)
0
1
0
clkI/O/8 (from prescaler)
0
1
clkI/O/64 (from prescaler)
1
0
clkI/O/256 (from prescaler)
1
0
1
clkI/O/1024 (from prescaler)
1
0
External clock source on Tn pin. Clock on falling edge.
1
External clock source on Tn pin. Clock on rising edge.
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