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參數(shù)資料
| 型號(hào)： | S75NS128ND0ZFWNK0 |
| 廠商： | Spansion Inc. |
| 英文描述： | 1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| 中文描述： | 1.8伏只，堆疊多芯片產(chǎn)品（MCP）的x16 MirrorBit閃存和DRAM |
| 文件頁數(shù)： | 4/211頁 |
| 文件大小： | 2858K |
| 代理商： | S75NS128ND0ZFWNK0 |
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2
S75NS128NDE based MCPs
S75NS128NDE_00_A2 September 23, 2005
A d v a n c e I n f o r m a t i o n
S75NS128NDE Based MCPs
Notice On Data Sheet Designations . . . . . . . . . . . ii
Advance Information ..............................................................ii
Preliminary ..........................................................................................................ii
Combination .......................................................................................................ii
Full Production (No Designation on Document) ...................................ii
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 1
MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 10
S29NS-N MirrorBit
TM
Flash Module
General Description . . . . . . . . . . . . . . . . . . . . . . . 12
Product Selector Guide . . . . . . . . . . . . . . . . . . . . 14
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 17
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .18
$<>1 <9
VersatileIO (V
IO
) Control .............................................................................18
Requirements for Asynchronous Read Operation (Non-Burst) ..........18
Requirements for Synchronous (Burst) Read Operation .......................19
Continuous Burst ............................................................................................19
$@D!8!A. <G
$=H.<G
$H=.@:
$A@.@:
$8I>D!8!A.
@:
$DI>H.@:
$9I>=. @:
$GI>@. @<
8-, 16-, and 32-Word Linear Burst with Wrap Around ......................21
$<:> @<
8-, 16-, and 32-Word Linear Burst without Wrap Around ................21
Programmable Wait State ...............................................................................22
Configuration Register .....................................................................................22
Handshaking Feature .........................................................................................22
Simultaneous Read/Write Operations with Zero Latency ...................22
Writing Commands/Command Sequences ................................................22
Accelerated Program and Erase Operations .............................................22
Write Buffer Programming Operation .........................................................23
Autoselect Mode ................................................................................................24
Advanced Sector Protection and Unprotection .......................................24
Sector Protection ................................................................................................25
Persistent Sector Protection ...........................................................................25
Persistent Protection Bit (PPB) .................................................................26
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector
Protection Mode ............................................................................................26
Dynamic Protection Bit (DYB) ..................................................................26
$<< @D
Persistent Sector Protection Mode Lock Bit .............................................27
Password Sector Protection ...........................................................................28
64-bit Password ..................................................................................................28
Password Mode Lock Bit .................................................................................28
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Pro-
tection Mode ........................................................................................................29
Hardware Data Protection Mode .................................................................29
Write Protect (WP#) ...................................................................................29
WP# Boot Sector Protection .........................................................................29
Low VCC Write Inhibit ....................................................................................30
Write Pulse “Glitch” Protection ....................................................................30
Logical Inhibit .......................................................................................................30
Power-Up Write Inhibit ...............................................................................30
Lock Register .......................................................................................................30
$<@; =:
Automatic Sleep Mode ......................................................................................31
RESET#: Hardware Reset Input ......................................................................31
V
CC
Power-up and Power-down Sequencing ........................................31
Output Disable Mode ........................................................................................31
Secured Silicon Sector Flash Memory Region ............................................31
Factory Locked: Factor Secured Silicon Sector Programmed and Pro-
tected At the Factory ...................................................................................32
$<=
Customer Secured Silicon Sector .............................................................32
Common Flash Memory Interface (CFI) . . . . . . 33
$<H,3 =H
$<A=H
$<8 =A
$<D 0"-)3 =A
$<9$!@G/@A8/ =D
$<G$!@G/<@9/ H<
Command Definitions . . . . . . . . . . . . . . . . . . . . . .44
Reading Array Data ...........................................................................................44
Set Configuration Register Command Sequence .....................................44
Read Configuration Register Command Sequence ..................................44
Read Mode Setting .........................................................................................45
Programmable Wait State Configuration ...............................................45
$@: $.HA
Programmable Wait State ...........................................................................45
$@<.2 HA
Handshaking .....................................................................................................46
Burst Length Configuration .........................................................................46
$@@> H8
Burst Wrap Around ......................................................................................46
RDY Configuration ........................................................................................46
RDY Polarity ....................................................................................................46
Configuration Register . . . . . . . . . . . . . . . . . . . . . .47
$@=;HD
Reset Command .................................................................................................47
$@H HG
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-
quence ....................................................................................................................49
Unlock Bypass Command Sequence ........................................................50
Program Command Sequence ........................................................................50
Program Command Sequence ....................................................................50
Program Command Sequence (Unlock Bypass Mode) .......................50
Accelerated Program ........................................................................................50
,< 1A<
Write Buffer Programming Command Sequence ......................................51
$@A.># A@
,@.> 1 A=
Chip Erase Command Sequence ...................................................................53
Chip Erase Command Sequence ...............................................................53
Sector Erase Command Sequence ................................................................54
Sector Erase Command Sequence ............................................................54
Accelerated Sector Erase ............................................................................55
=@
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S75NS128ND0ZFWNK2 | 1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| S75NS128ND0ZFWNK3 | 1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| S75NS128ND0ZJWNJ0 | 1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| S75NS128ND0ZJWNJ2 | 1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| S75NS128ND0ZJWNJ3 | 1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S75NS128ND0ZFWNK2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| S75NS128ND0ZFWNK3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| S75NS128ND0ZJWNJ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| S75NS128ND0ZJWNJ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
| S75NS128ND0ZJWNJ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit Flash Memory and DRAM |
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