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參數(shù)資料
| 型號： | S75NS128NBFJWJZ3 |
| 廠商： | Spansion Inc. |
| 英文描述： | MirrorBit 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) |
| 中文描述： | 1.8伏的MirrorBit只同步讀/寫，突發(fā)模式復用閃存（NOR接口） |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 221K |
| 代理商： | S75NS128NBFJWJZ3 |
S75NS-N_00_01E May 3, 2006
S75NS-N
3
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
2.
Input/Output Descriptions
Table 2.1
identifies the input and output package connections provided on the device.
Table 2.1
Input/Output Descriptions
Symbol
Signal
Type
Description
NS
(NOR)
pSRAM
MS
(ORNAND)
AMAX – A16
Input
Address inputs
X
X
ADQ15 – ADQ0
I/O
Multiplexed Address/Data
X
X
OE#
Input
Output Enable input. Asynchronous relative to CLK for the Burst
mode.
X
X
WE#
Input
Write Enable input.
X
X
V
SS
Ground
Ground
X
X
F-RDY / R-WAIT
Output
Ready output. Indicates the status of the Burst read. The WAIT#
pin of the pSRAM is tied to RDY.
X
X
CLK
Input
Clock input. In burst mode, after the initial word is output,
subsequent active edges of CLK increment the internal address
counter. Should be at V
IL
or V
IH
while in asynchronous mode
X
X
AVD#
Input
Address Valid input. Indicates to device that the valid address is
present on the address inputs. Low = for asynchronous mode,
indicates valid address; for burst mode, causes starting address
to be latched. High = device ignores address inputs
X
X
F-RST#
Input
Hardware reset input. Low = device resets and returns to reading
array data
X
F-WP#
Input
Hardware write protect input. At V
, disables program and erase
functions in the four outermost sectors. Should be at V
IH
for all
other conditions.
X
F-ACC
Input
Accelerated input. At V
, accelerates programming;
automatically places device in unlock bypass mode. At V
IL
,
disables all program and erase functions. Should be at V
IH
for all
other conditions.
X
F-CE#
Input
Chip-enable input for Flash. Asynchronous relative to CLK for
Burst Mode.
X
V
CC
Power
Flash 1.8 Volt-only single power supply
X
X
R-CE1#
Input
Chip-enable input for pSRAM
X
R-CRE
Input
Control Register Enable (pSRAM)
X
R-V
CC
Power
pSRAM Power Supply
X
R-UB#
Input
Upper Byte Control (pSRAM)
X
R-LB#
Input
Lower Byte Control (pSRAM)
X
N-CLE
Input
Command Latch Enable
X
N-ALE
Input
Address Latch Enable
X
N-CE#
Input
Chip Enable input for ORNAND
X
N-WE#
Input
Write Enable input
X
N-RE#
Input
Read Enable input
X
N-IO0 - N-IO7
I/O
Data Input/Output
X
N-WP#
Input
Hardware write protect input. At V
, disables program and erase
functions in the four outermost sectors. Should be at V
IH
for all
other conditions.
X
N-RY/BY#
Input
Ready/Busy output
X
N-PRE
Input
Power-On Read Enable
X
N-V
SS
Ground
Ground
X
N-V
CC
Power
ORNAND 1.8 Volt-only single power supply.
X
DNU
—
Do Not Use
NC
—
No Connect; not connected internally
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相關代理商/技術參數(shù) |
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| S75NS128NBG | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) |
| S75NS128NBGJWJZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) |
| S75NS128NBGJWJZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) |
| S75NS128NBGJWJZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) |
| S75NS128NCFJWJZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) |
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