參數(shù)資料
型號(hào)： S72WS512PD0HF0HG2
廠商： Spansion Inc.
英文描述： based MCP/PoP Products
中文描述： 基于MCP的/流行產(chǎn)品
文件頁(yè)數(shù)： 10/17頁(yè)
文件大?。?/td> 518K
代理商： S72WS512PD0HF0HG2
8
S72WS-P based MCP/PoP Products
S72WS-P_00_A4 May 29, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
3.3
NOR Flash and DRAM Input/Output Descriptions
3.3.1
ORNAND Signal Descriptions
Amax-A0
=
NOR Flash Address inputs
DQ15-DQ0
=
Flash Data input/output, shared between NOR and ORNAND Flash. DQ0-DQ7 shared for x8 ORNAND
F-CE#
=
NOR Flash Chip-enable input #1. Asynchronous relative to CLK for Burst Mode.
F-OE#
=
NOR Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
F-WE#
=
NOR Flash Write Enable input.
F-V
CC
F-V
CCQ
=
NOR Flash device power supply (1.7 V - 1.95V).
=
Input/Output Buffer power supply.
V
SS
=
Ground
RFU
=
Reserved for Future Use
F-RDY
=
Flash ready output. Indicates the status of the Burst read. VOL = data valid.
F-CLK
=
NOR Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input
and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK
increment the internal address counter. CLK should remain low during asynchronous access.
F-AVD#
=
NOR Flash Address Valid input. Indicates to device that the valid address is present on the address
inputs.
VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be
latched on rising edge of CLK.
VIH= device ignores address inputs
F-RST#
=
NOR Flash hardware reset input. VIL= device resets and returns to reading array data
F-WP#
=
NOR Flash hardware write protect input. VIL = disables program and erase functions in the four
outermost sectors.
F-ACC
=
NOR Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.
D-Amax-D-A0
=
SDRAM Address inputs
D-DQ15-D-DQ0
=
SDRAM Data input/output
D-CLK
=
SDRAM System Clock
D-CE#
=
SDRAM Chip Select
D-CKE
=
SDRAM Clock Enable
D-BA1-BA0
=
SDRAM Bank Select
D-RAS#
=
SDRAM Row Address Strobe
D-CAS#
=
SDRAM Column Address Strobe
D-DM1-D-DM0
=
SDRAM Data Input/Output Mask
D-WE#
=
SDRAM Write Enable input
D-V
SS
=
SDRAM Ground
D-CLK#
=
DDR SDRAM Clock - in addition to D-CLK, this signal is available for DDRAMs that need CLK# for
normal operations
D-V
SSQ
D-V
CCQ
=
SDRAM Input/Output Buffer ground
=
SDRAM Input/Output Buffer power supply
D-V
CC
=
SDRAM device power supply
D-DQS0 - D-
DQS1
=
DDR SDRAM Data Strobe pins. DQS provides the read data strobes (as output) and the write data
strobes (as input). Each DQS pin corresponds to eight DQ pins, respectively.
N-PRE
N-ALE
N-CLE
N-CE#
N-WP#
N-WE#
N-RE#
N-RY/BY#
N-I/O0-N-I/O15
N-V
CC
=
=
=
=
=
=
=
=
=
=
ORNAND Power-On Read Enable. Tie to V
SS
on customer board if not used
ORNAND Address Latch Enable
ORNAND Command Latch Enable
ORNAND Chip-enablE
ORNAND Write-protect
ORNAND Write-enable
ORNAND Read-enable
ORNAND Ready-Busy
ORNAND I/O Signals (I/O0-I/O7 for x8 bus width)
ORNAND Power Supply
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