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參數(shù)資料
| 型號： | S72WS512NFGBAW4Y2 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Based MCP/PoP Products |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA137 |
| 封裝： | 11 X 13 MM, 1.40 MM HEIGHT, LEAD FREE COMPLIANT, FBGA-137 |
| 文件頁數(shù)： | 16/30頁 |
| 文件大?。?/td> | 810K |
| 代理商： | S72WS512NFGBAW4Y2 |
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14
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e I n f o r m a t i o n
3.8
NOR Flash and DRAM Input/Output Descriptions
A23-A0
=
DQ15-DQ0
=
NOR Flash Address inputs
Flash Data input/output, shared between NOR and ORNAND
Flash. DQ0-DQ7 shared for x8 ORNAND
NOR Flash Chip-enable input # 2. Asynchronous relative to CLK
for burst mode.
NOR Flash Chip-enable input #1. Asynchronous relative to CLK
for Burst Mode.
NOR Flash Output Enable input. Asynchronous relative to CLK
for Burst mode.
NOR Flash Write Enable input.
NOR Flash device power supply (1.7 V - 1.95V).
Input/Output Buffer power supply.
Ground
Reserved for Future Use
Flash ready output. Indicates the status of the Burst read. VOL
= data valid. Shared between NOR and ORNAND Flash.
NOR Flash Clock. The first rising edge of CLK in conjunction with
AVD# low latches the address input and activates burst mode
operation. After the initial word is output, subsequent rising
edges of CLK increment the internal address counter. CLK
should remain low during asynchronous access.
NOR Flash Address Valid input. Indicates to device that the valid
address is present on the address inputs.
VIL = for asynchronous mode, indicates valid address; for burst
mode, causes starting address to be latched on rising edge of
CLK.
VIH= device ignores address inputs
NOR Flash hardware reset input. VIL= device resets and returns
to reading array data
NOR Flash hardware write protect input. VIL = disables program
and erase functions in the four outermost sectors.
NOR Flash accelerated input. At VHH, accelerates
programming; automatically places device in unlock bypass
mode. At VIL, disables all program and erase functions. Should
be at VIH for all other conditions.
SDRAM Address inputs
SDRAM Data input/output
SDRAM System Clock
SDRAM Chip Select
SDRAM Clock Enable
SDRAM Bank Select
SDRAM Row Address Strobe
SDRAM Column Address Strobe
SDRAM Data Input/Output Mask
SDRAM Write Enable input
SDRAM Ground
SDRAM Input/Output Buffer ground
SDRAM Input/Output Buffer power supply
SDRAM device power supply
F2-CE#
=
F1-CE#
=
OE#
=
F-WE#
F-V
CC
F-V
CC
q
V
SS
RFU
RDY
=
=
=
=
=
=
CLK
=
AVD#
=
F-RST#
=
F-WP#
=
F-ACC
=
D-A12-D-A0
D-DQ15-D-DQ0
D-CLK
D-CE#
D-CKE
D-BA1-BA0
D-RAS#
D-CAS#
D-DM1-D-DM0
D-WE#
D-VSS
D-VSSQ
D-VCCQ
D-VCC
=
=
=
=
=
=
=
=
=
=
=
=
=
=
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相關代理商/技術參數(shù) |
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|---|---|
| S72WS512NFGBAW4Y3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCP/PoP Products |
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| S72WS512NFGKFW4Y0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCP/PoP Products |
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