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參數(shù)資料
| 型號(hào)： | S71WS512N80BFWZZ2 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁(yè)數(shù)： | 72/142頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BFWZZ2 |
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72
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
S71WS512NE0BFWZZ_00_ A1 June 28, 2004
A d v a n c e I n f o r m a t i o n
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. But DQ2 cannot distinguish whether the sector is ac-
tively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to
Table 19
to compare outputs for DQ2 and DQ6.
See the following for additional information:
Figure 6
, the "
DQ6: Toggle Bit I
" sec-
tion, and
Figure 25
.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7–
DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the new value of the tog-
gle bit with the first. If the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read array data on DQ7–DQ0 on
the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
Table 19. DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
actively erasing,
at an address within a sector
selected for erasure,
toggles,
also toggles.
at an address within sectors
not
selected for erasure,
toggles,
does not toggle.
erase suspended,
at an address within a sector
selected for erasure,
does not toggle,
toggles.
at an address within sectors
not
selected for erasure,
returns array data,
returns array data. The system can read
from any sector not selected for erasure.
programming in
erase suspend
at any address,
toggles,
is not applicable.
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相關(guān)代理商/技術(shù)參數(shù) |
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| S71WS512N80BFWZZ3 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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