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參數(shù)資料
| 型號(hào)： | S71WS512N80BAWZZ0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁(yè)數(shù)： | 110/142頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BAWZZ0 |
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110
128Mb pSRAM
S71WS512NE0BFWZZ_00_A1 June 28, 2004
P r e l i m i n a r y
AC CHARACTERISTICS
(Under Recommended Operating Conditions unless otherwise noted)
ASYNCHRONOUS READ OPERATION (PAGE MODE)
Notes
*1: Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A22.
If needed by system operation, please contact local FUJITSU representative for the relaxation of 1ms
limitation.
*2: Address Should Not Be Changed Within Minimum T
rc
.
*3: The output load 50pF with 50ohm termination to V
DDQ
*0.5 V.
*4: The output load 5pF without any other load.
*5: Applicable to A3 to A22 when CE#1 is kept at Low.
*6: Applicable only to A0, A1 and A2 when CE#1 is kept at Low for the page address access.
*7: In case Page Read Cycle is continued with keeping CE#1 stays Low, CE#1 must be brought to High within
4ms. In other words, Page Read Cycle must be closed within 4ms.
*8: t
VPL
is specified from the negative edge of either CE#1 or ADV# whichever comes late.
*9: Applicable when at least two of address inputs among applicable are switched from previous state.
*10: t
RC
(min) and t
PRC
(min) must be satisfied.
Parameter
Symbol
Value
Unit
Notes
Min.
Max.
Read Cycle Time
t
RC
70
1000
ns
*1, *2
CE#1 Access Time
t
CE
—
70
ns
*3
OE# Access Time
t
OE
—
40
ns
*3
Address Access Time
t
AA
—
70
ns
*3, *5
ADV# Access Time
t
AV
70
ns
*3
LB#, UB# Access Time
t
BA
—
30
ns
*3
Page Address Access Time
t
PAA
—
20
ns
*3, *6
Page Read Cycle Time
t
PRC
20
1000
ns
*1, *6, *7
Output Data Hold Time
t
OH
5
—
ns
*3
CE#1 Low to Output Low-Z
t
CLZ
5
—
ns
*4
OE# Low to Output Low-Z
t
OLZ
0
—
ns
*4
LB#, UB# Low to Output Low-Z
t
BLZ
0
—
ns
*4
CE#1 High to Output High-Z
t
CHZ
—
20
ns
*3
OE# High to Output High-Z
t
OHZ
—
20
ns
*3
LB#, UB# High to Output High-Z
t
BHZ
—
20
ns
*3
Address Setup Time to CE#1 Low
t
ASC
–5
—
ns
Address Setup Time to OE# Low
t
ASO
10
—
ns
ADV# Low Pulse Width
t
VPL
10
—
ns
*8
Address Hold Time from ADV# High
t
AHV
5
—
ns
Address Invalid Time
t
AX
—
10
ns
*5, *9
Address Hold Time from CE#1 High
t
CHAH
–5
—
ns
*10
Address Hold Time from OE# High
t
OHAH
–5
—
ns
CE#1 High Pulse Width
t
CP
15
—
ns
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| S71WS512N80BFEZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| S71WS512N80BAWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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