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參數(shù)資料
| 型號(hào)： | S71WS256PD0KF3SV0 |
| 廠商： | Spansion Inc. |
| 英文描述： | 1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode Flash Memory with CellularRAM |
| 中文描述： | 1.8伏只x16同步讀/寫(xiě)，突發(fā)模式CellularRAM的閃存記憶體與 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | S71WS256PD0KF3SV0 |
4
S71WS-P based MCP Products
S71WS-P_00_A2 August 21, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
3.3
NOR Flash and pSRAM Input/Output Descriptions
Amax-A0
=
NOR Flash Address inputs
DQ15-DQ0
=
Flash Data input/output, shared between NOR and ORNAND Flash. DQ0-DQ7 shared for x8 ORNAND
F-CE#
=
NOR Flash Chip-enable input #1. Asynchronous relative to CLK for Burst Mode.
OE#
=
Output Enable input. Asynchronous relative to CLK for Burst mode.
WE#
=
Write Enable input.
F-V
CC
F-V
CCQ
=
NOR Flash device power supply (1.7 V - 1.95V).
=
Input/Output Buffer power supply.
V
SS
=
Ground
RFU
=
Reserved for Future Use
RDY
=
Flash ready output. Indicates the status of the Burst read. VOL = data valid. The Flash RDY pin is shared
with the WAIT pin of the pSRAM.
CLK
=
NOR Flash Clock, shared with CLK of burst-mode pSRAM.. The first rising edge of CLK in conjunction
with AVD# low latches the address input and activates burst mode operation. After the initial word is
output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low
during asynchronous access.
AVD#
=
NOR Flash Address Valid input. Shared with AVD# of burst-mode pSRAM. Indicates to device that the
valid address is present on the address inputs.
VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be
latched on rising edge of CLK.
VIH= device ignores address inputs
F-RST#
=
NOR Flash hardware reset input. VIL= device resets and returns to reading array data
F-WP#
=
NOR Flash hardware write protect input. VIL = disables program and erase functions in the four
outermost sectors.
F-ACC
=
NOR Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.
R-CE#
=
Chip-enable input for pSRAM
R-CRE
=
Control Register Enable (pSRAM). For CellularRAM only.
R-VCC
=
pSRAM Power Supply
R-UB#
=
Upper Byte Control (pSRAM)
R-LB#
=
Lower Byte Control (pSRAM)
DNU
=
Do Not Use
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS256PD0KF3SV2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode Flash Memory with CellularRAM |
| S71WS256PD0KF3SV3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode Flash Memory with CellularRAM |
| S71WS256PD0KFFLW0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:based MCP/POP Products |
| S71WS256PD0KFFLW2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:based MCP/POP Products |
| S71WS256PD0KFFLW3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:based MCP/POP Products |
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